41.7.14 CSI Packet Fatal Error Interrupt Status Register
Notifies which interrupt bit has caused the interruption.
Reading CSI_INT_ST_PKT_FATAL does not clear the interrupt pin.
The following configuration values are valid for all listed bit names of this register:
0: No event occurred since the last read of the register.
1: An event occurred since the last read of the register.
| Name: | CSI_INT_ST_PKT_FATAL |
| Offset: | 0xF0 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ERR_ECC_DOUBLE | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VC3_ERR_CRC | VC2_ERR_CRC | VC1_ERR_CRC | VC0_ERR_CRC | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |