35.17.28 PMC MCK0 Monitor Limits Register

Name: PMC_MCKLIM
Offset: 0x009C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 MCK_HIGH_IT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 MCK_LOW_IT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:8 – MCK_HIGH_IT[7:0] MCK0 Monitoring High IT Limit

Beyond this limit, the MCK0 frequency monitor generates an interrupt.

Bits 7:0 – MCK_LOW_IT[7:0] MCK0 Monitoring Low IT Limit

Below this limit, the MCK0 frequency monitor generates an interrupt.