35.17.4 PMC PLL Control Register 0

All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.

Name:	PMC_PLL_CTRL0
Offset:	0x000C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	ENLOCK	ENIOPLLCK	ENPLLCK	ENPLL
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0


Bit	23	22	21	20	19	18	17	16
					DIVIO[7:4]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DIVIO[3:0]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DIVPMC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – ENLOCK Enable PLL Lock

Value	Description
0	The lock signal sent by the PLL is ignored. The PLL is considered as locked once the start-up time defined by PMC_PLL_UPDT.STUPTIM has elapsed.
1	The PLL is considered as locked once the start-up time defined by PMC_PLL_UPDT.STUPTIM has elapsed and the lock signal sent by the PLL has risen.

Bit 30 – ENIOPLLCK Enable PLL Clock for IO

This feature is available for AUDIOPLL only. If the DIVIO field is equal to 0, this bit can be used to enable or disable the PLL clock on the IO. If DIVIO is not equal to 0, the PLL clock on the IO is always active.

Value	Description
0	The clock generated by the PLL is not sent to the IO.
1	The clock generated by the PLL is sent to the IO.

Bit 29 – ENPLLCK Enable PLL Clock for PMC

This feature is available for all PLLs. If the DIVPMC field is equal to 0, this bit can be used to enable or disable the PLL clock to the PMC. If DIVPMC is not equal to 0, the PLL clock to the PMC is always active.

Value	Description
0	The clock generated by the PLL is not send to the PMC.
1	The clock generated by the PLL is sent to the PMC.

Bit 28 – ENPLL Enable PLL

Value	Description
0	The PLL is off.
1	The PLL is on.

Bits 19:12 – DIVIO[7:0] Divider for PAD

Specifies the division ratio applied to the internal PLL clock before being sent to the IO. This feature is not available for all PLLs. Refer to PLL characteristics in the section “Electrical Characteristics” for more information. This feature is only available for AUDIOPLL. The frequency is defined by the following formula:

f_{IOPLLCK} = \frac{f_{COREPLLCK}}{(DIVIO + 1)}

Bits 7:0 – DIVPMC[7:0] Divider for PMC

Specifies the division ratio applied to the internal PLL clock before being sent to the PMC. The frequency is defined by the following formula:

f_{PLL Clock} = \frac{f_{COREPLLCK}}{(DIVPMC + 1)}