35.17.30 PMC Peripheral Clock Status Register 1
The following configuration values are valid for all listed bit names of this
register:
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
| Name: | PMC_CSR1 |
| Offset: | 0x00A4 |
| Reset: | 0x00000000 |
| Property: | Read-only |
“PIDx” refers to
identifiers as defined in the table “Peripheral Identifiers”.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | PID63 | PID62 | PID61 | PID60 | | PID58 | PID57 | PID56 | |
| Access | R | R | R | R | | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | PID55 | | | PID52 | PID51 | | PID49 | PID48 | |
| Access | R | | | R | R | | R | R | |
| Reset | 0 | | | 0 | 0 | | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | PID47 | PID46 | PID45 | PID44 | PID43 | PID42 | PID41 | PID40 | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | PID39 | PID38 | PID37 | | | PID34 | PID33 | PID32 | |
| Access | R | R | R | | | R | R | R | |
| Reset | 0 | 0 | 0 | | | 0 | 0 | 0 | |
Bits 28, 29, 30, 31 – PIDx Peripheral Clock x Status
Bits 23, 24, 25, 26 – PIDx Peripheral Clock x Status
Bits 19, 20 – PIDx Peripheral Clock x Status
Bits 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PIDx Peripheral Clock x Status
Bits 0, 1, 2 – PIDx Peripheral Clock x Status
