35.17.9 PMC Clock Generator Main Oscillator Register
This register can only be written if the WPEN bit is cleared in the PMC Write
Protection Mode Register.
Note: Bit 5 is always read at 1.
| Name: | CKGR_MOR |
| Offset: | 0x0020 |
| Reset: | 0x00000028 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AUTOCPUSW | AUTOMAINSW | XT32KFME | CFDEN | MOSCSEL | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| KEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MOSCXTST[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ULP2 | MOSCRCEN | ULP1 | MOSCXTEN | ||||||
| Access | W | R/W | W | R/W | |||||
| Reset | 0 | 1 | 0 | 0 |
Bit 30 – AUTOCPUSW Automatic Processor Clock Source Switching
| Value | Description |
|---|---|
| 0 | A main crystal oscillator failure detection has no effect on the processor clock source selection. |
| 1 | If a main crystal oscillator failure is detected, the processor clock source selection automatically switches to the main clock. |
Bit 29 – AUTOMAINSW Automatic Main Clock Source Switching
| Value | Description |
|---|---|
| 0 | A main crystal oscillator failure detection has no effect on the main clock source selection. |
| 1 | If a main crystal oscillator failure is detected, the main clock source selection automatically switches to the main RC. |
Bit 26 – XT32KFME 32.768 kHz Crystal Oscillator Frequency Monitoring Enable
| Value | Description |
|---|---|
| 0 | The 32.768 kHz crystal oscillator frequency monitoring is disabled. |
| 1 | The 32.768 kHz crystal oscillator frequency monitoring is enabled. |
Bit 25 – CFDEN Clock Failure Detector Enable
| Value | Description |
|---|---|
| 0 | The clock failure detector is disabled. |
| 1 | The clock failure detector is enabled. |
Bit 24 – MOSCSEL Main Clock Oscillator Selection
| Value | Description |
|---|---|
| 0 | The main RC oscillator is selected. |
| 1 | The main crystal oscillator is selected. |
Bits 23:16 – KEY[7:0] Write Access Password
| Value | Name | Description |
|---|---|---|
| 0x37 | PASSWD | Writing any other value in this field aborts the write operation. Always reads as 0. |
Bits 15:8 – MOSCXTST[7:0] Main Crystal Oscillator Start-up Time
Specifies the number of MD_SLCK cycles multiplied by 8 for the main crystal oscillator start-up time.
Bit 7 – ULP2 ULP2 Mode Command (write-only)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the device to enter ULP2 mode. ULP2 mode is entered when the processor WFE instruction is executed. |
Bit 3 – MOSCRCEN Main RC Oscillator Enable
When MOSCRCEN is set, the MOSCRCS flag is set once the main RC oscillator start-up time is achieved.
| Value | Description |
|---|---|
| 0 | The main RC oscillator is disabled. |
| 1 | The main RC oscillator is enabled. |
Bit 2 – ULP1 ULP1 Mode Command (write-only)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Puts the device in ULP1 mode. |
Bit 0 – MOSCXTEN Main Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT or a clock signal must be provided on XIN with XOUT grounded.
When MOSCXTEN is set, the MOSCXTS flag is set once the main crystal oscillator start-up time is achieved.
| Value | Description |
|---|---|
| 0 | The main crystal oscillator is disabled. |
| 1 | The main crystal oscillator is enabled or in bypass. |