35.17.35 PMC Generic Clock Status Register 2
The following configuration values are valid for all listed bit names of
this register:
0: The corresponding generic clock is disabled.
1: The corresponding generic clock is enabled.
| Name: | PMC_GCSR2 |
| Offset: | 0x00C8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
“PIDx” refers to
identifiers as defined in the table “Peripheral Identifiers”.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | GPID95 | GPID94 | | | GPID91 | | | GPID88 | |
| Access | R | R | | | R | | | R | |
| Reset | 0 | 0 | | | 0 | | | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | GPID85 | GPID84 | | GPID82 | GPID81 | GPID80 | |
| Access | | | R | R | | R | R | R | |
| Reset | | | 0 | 0 | | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | GPID79 | GPID78 | | | GPID75 | GPID74 | GPID73 | GPID72 | |
| Access | R | R | | | R | R | R | R | |
| Reset | 0 | 0 | | | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | GPID71 | GPID70 | GPID69 | GPID68 | | GPID66 | GPID65 | GPID64 | |
| Access | R | R | R | R | | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | |
Bits 30, 31 – GPIDx Generic Clock x Status
Bit 27 – GPIDx Generic Clock x Status
Bit 24 – GPIDx Generic Clock x
Status
Bits 20, 21 – GPIDx Generic Clock x
Status
Bits 14, 15, 16, 17, 18 – GPIDx Generic Clock x
Status
Bits 4, 5, 6, 7, 8, 9, 10, 11 – GPIDx Generic Clock x
Status
Bits 0, 1, 2 – GPIDx Generic Clock x
Status
