35.17.32 PMC Peripheral Clock Status Register 3
The following configuration values are valid for all listed bit names of
this register:
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
| Name: | PMC_CSR3 |
| Offset: | 0x00AC |
| Reset: | 0x00000000 |
| Property: | Read-only |
“PIDx” refers to
identifiers as defined in the table “Peripheral Identifiers”.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | PID106 | PID105 | PID104 | |
| Access | | | | | | R | R | R | |
| Reset | | | | | | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | PID98 | PID97 | PID96 | |
| Access | | | | | | R | R | R | |
| Reset | | | | | | 0 | 0 | 0 | |
Bits 8, 9, 10 – PIDx Peripheral Clock x
Status
Bits 0, 1, 2 – PIDx Peripheral Clock x
Status
