35.17.31 PMC Peripheral Clock Status Register 2
The following configuration values are valid for all listed bit names of
this register:
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
| Name: | PMC_CSR2 |
| Offset: | 0x00A8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
“PIDx” refers to
identifiers as defined in the table “Peripheral Identifiers”.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | PID95 | PID94 | PID93 | PID92 | PID91 | PID90 | PID89 | PID88 | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | PID87 | PID86 | PID85 | PID84 | PID83 | PID82 | PID81 | PID80 | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | PID79 | PID78 | PID77 | | PID75 | PID74 | PID73 | PID72 | |
| Access | R | R | R | | R | R | R | R | |
| Reset | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | PID71 | PID70 | PID69 | PID68 | | PID66 | PID65 | PID64 | |
| Access | R | R | R | R | | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | |
Bits 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x
Status
Bits 4, 5, 6, 7, 8, 9, 10, 11 – PIDx Peripheral Clock x
Status
Bits 0, 1, 2 – PIDx Peripheral Clock x
Status
