Note: This register cannot be modified while PGxSTAT.UPDATE =
1.
Table 14-33. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
PGxDT
Offset:
0x1090, 0x10D8, 0x1120,
0x1168
Bit
31
30
29
28
27
26
25
24
DTH[14:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DTH[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DTL[14:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DTL[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 30:16 – DTH[14:0] PWMx Dead-Time
Delay
Bits 14:0 – DTL[14:0] PWMxL Dead-Time Delay
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
