14.3.1 PWM Clock Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PCLKCON |
| Offset: | 0x1004 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVSEL[1:0] | MCLKSEL | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bit 8 – LOCK Lock
| Value | Description |
|---|---|
1 | Write-protected registers and bits are locked |
0 | Write-protected registers and bits are unlocked |
Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection
| Value | Description |
|---|---|
11 | Divide ratio is 1:16 |
10 | Divide ratio is 1:8 |
01 | Divide ratio is 1:4 |
00 | Divide ratio is 1:2 |
Bit 0 – MCLKSEL PWM Master Clock Selection
Note: Do not change the
MCLKSEL bit while ON (PGxCON[15]) =
1.See Table 14-2 for MCLKSEL PWM Master Clock Selection.