14.3.11 PWM Generator x Control Register
- This bit(s) cannot be modified while PGxCON.ON = 1.
- This bit(s) cannot be modified while UPDATE = 1.
- Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | PGxCON |
| Offset: | 0x1050, 0x1098, 0x10E0, 0x1128 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MDCSEL | MPERSEL | MPHSEL | MSTEN | UPDMOD[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRGMOD[1:0] | SOCS[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | FRZ | TRGCNT[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | CLKSEL[1:0] | MODSEL[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 31 – MDCSEL Master Duty Cycle Register Select(4)
| Value | Description |
|---|---|
1 | PWM Generator uses MDC register |
0 | PWM Generator uses PGxDC register |
Bit 30 – MPERSEL Master Period Register Select(4)
| Value | Description |
|---|---|
1 | PWM Generator uses MPER register |
0 | PWM Generator uses PGxPER register |
Bit 29 – MPHSEL Master Phase Register Select(4)
| Value | Description |
|---|---|
1 | PWM Generator uses MPHASE register |
0 | PWM Generator uses PGxPHASE register |
Bit 27 – MSTEN Master Update Enable(4)
| Value | Description |
|---|---|
1 | PWM Generator broadcasts software set of UPDREQ control bit and EOC signal to other PWM Generators |
0 | PWM Generator does not broadcast UPDREQ status bit state or EOC signal |
Bits 26:24 – UPDMOD[2:0] PWM Buffer Update Mode Selection
See Table 14-38 for details.
Bits 23:22 – TRGMOD[1:0] PWM Generator x Trigger Mode Selection(4)
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | Reserved |
| 01 | PWM Generator operates in Retriggerable mode |
| 00 | PWM Generator operates in Single Trigger mode |
Bits 19:16 – SOCS[3:0] Start-of-Cycle Selection bits(4)
- The PCI selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0] bits if the PCI Sync function is enabled.
- The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local PWM Generator. If not, the source must be routed through the PCI Sync logic so the trigger signal may be synchronized to the PWM Generator clock domain.
- PWM Generators are grouped into groups of four: PG1-PG4 and PG5-PG8, if available. Any generator within a group of four may be used to trigger another generator within the same group.
| Value | Description |
|---|---|
1111 |
TRIG bit or PCI Sync function only (no hardware trigger source is selected) |
1110 -
0101 |
Reserved |
0100 |
Trigger output selected by PG4 or PG8 PGTRGSEL[2:0] bits (PGxEVT[2:0]) |
0011 |
Trigger output selected by PG3 or PG7 PGTRGSEL[2:0] bits (PGxEVT[2:0]) |
0010 |
Trigger output selected by PG2 or PG6 PGTRGSEL[2:0] bits (PGxEVT[2:0]) |
0001 |
Trigger output selected by PG1 or PG5 PGTRGSEL[2:0] bits (PGxEVT[2:0]) |
0000 |
Local EOC – PWM Generator is self-triggered |
Bit 15 – ON PWM Generator x Enable(1)
| Value | Description |
|---|---|
1 |
PWM Generator is enabled |
0 |
PWM Generator is not enabled |
Bit 14 – FRZ FRZ PWM Freeze bit
| Value | Description |
|---|---|
1 |
PWM module stops operation in Debug mode |
0 |
PWM module continues operation in Debug mode |
Bits 10:8 – TRGCNT[2:0] PWM Generator x Trigger Count Select(1)
| Value | Description |
|---|---|
111 |
PWM Generator produces 8 PWM cycles after triggered |
110 |
PWM Generator produces 7 PWM cycles after triggered |
101 |
PWM Generator produces 6 PWM cycles after triggered |
100 |
PWM Generator produces 5 PWM cycles after triggered |
011 |
PWM Generator produces 4 PWM cycles after triggered |
010 |
PWM Generator produces 3 PWM cycles after triggered |
001 |
PWM Generator produces 2 PWM cycles after triggered |
000 |
PWM Generator produces 1 PWM cycle after triggered |
Bit 7 – Reserved
Bits 4:3 – CLKSEL[1:0] Clock Selection(1)
- Do not change the CLKSEL[1:0]
bits while ON (PGxCON[15]) =
1. - The PWM Generator time base operates from the frequency scaling circuit clock, effectively scaling the duty cycle and period of the PWM Generator output.
| Value | Description |
|---|---|
11 |
PWM Generator uses the master clock scaled by the frequency scaling circuit(2) |
10 |
PWM Generator uses the master clock divided by the clock divider circuit(2) |
01 |
PWM Generator uses the master clock selected by the MCLKSEL (PCLKCON[0]) control bits |
00 |
No clock selected, PWM Generator is in the lowest power state (default) |
Bits 2:0 – MODSEL[2:0] PWM Generator x Mode Selection(1)
| Value | Description |
|---|---|
111 |
Dual Edge Center-Aligned PWM mode (interrupt/register update twice per cycle) |
110 |
Dual Edge Center-Aligned PWM mode (interrupt/register update once per cycle) |
101 |
Double Update Center-Aligned PWM mode |
100 |
Center-Aligned PWM mode |
011 |
Reserved |
010 |
Independent Edge PWM mode, dual output |
001 |
Variable Phase PWM mode |
000 |
Independent Edge PWM mode |