18.2.1 Architecture Overview

The timer is an APB_0 slave that provides two programmable, interrupt generating, 32-bit decrementing counters, as shown in the following figure.

The Timer has an APB interface through which the Cortex-M3 processor can access various control and status registers to control and monitor the operation of the Timer. The Timer consists of two 32-bit decrementing counters. Counters generate the interrupts TIMER1INTand TIMER2INT on reaching zero. Refer to the 18.4 Timer Register Map for more information on Timer registers.