18.2.2 Port List

The following table lists the Timer ports.

Table 18-1. Timer Interface Signals
Name	Type	Width	Description
TIMER1INT	Output	1	Active high interrupt from counter 1. If enabled, this interrupt is asserted when counter 1 reaches zero. In 64-bit mode, this interrupt line is asserted when the  64-bit counter reaches zero.
TIMER2INT	Output	1	Active-high interrupt from counter 2. If enabled, this interrupt is asserted when counter 2 reaches zero.

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