18.4 Timer Register Map
The following table summarizes each of the Timer registers described in this document. The Timer base address resides at 0x40004000 and extends to address 0x40004FFF in the Cortex-M3 processor memory map.
| Register Name | Address Offset | R/W | Reset Value | Description |
|---|---|---|---|---|
| TIM1_VAL (Table 18-5) | 0x00 | R | 0 | Current value of Timer1 |
| TIM1_LOADVAL (Table 18-6) | 0x04 | R/W | 0 | Load value for Timer1 |
| TIM1_BGLOADVAL (Table 18-7) | 0x08 | R/W | 0 | Background load value for Timer1 |
| TIM1_CTRL (Table 18-8) | 0x0C | R/W | 0 | Control register for Timer1 |
| TIM1_RIS (Table 18-9) | 0x10 | R/W | 0 | Timer 1 raw interrupt status |
| TIM1_MIS (Table 18-10) | 0x14 | R | 0 | Timer 1 masked interrupt status |
| TIM2_VAL (Table 18-5) | 0x18 | R | 0 | Current value of Timer2 |
| TIM2_LOADVAL (Table 18-6) | 0x1C | R/W | 0 | Load value for Timer2 |
| TIM2BGLOADVAL (Table 18-7) | 0x20 | R/W | 0 | Background load value for Timer2 |
| TIM2_CTRL (Table 18-8) | 0x24 | R/W | 0 | Control register for Timer2 |
| TIM2_RIS (Table 18-9) | 0x28 | R/W | 0 | Timer2 raw interrupt status |
| TIM2MIS (Table 18-10) | 0x2C | R | 0 | Timer2 masked interrupt status |
| Table 18-11 | 0x30 | R | 0 | Upper 32-bit word for 64-bit mode |
| Table 18-12 | 0x34 | R | 0 | Lower 32-bit word for 64-bit mode |
| TIM64_LOADVAL_U (Table 18-11) | 0x38 | R/W | 0 | Upper 32-bit word for 64-bit mode immediate load |
| Table 18-14 | 0x3C | R/W | 0 | Lower 32-bit word for 64-bit mode immediate load |
| Table 18-15 | 0x40 | R/W | 0 | Upper 32-bit word for background value for 64-bit mode |
| Table 18-16 | 0x44 | R/W | 0 | Lower 32-bit word for background value for 64-bit mode |
| Table 18-17 | 0x48 | R/W | 0 | Control register for 64-bit mode |
| Table 18-18 | 0x4C | R/W | 0 | Raw interrupt status for 64-bit mode |
| Table 18-19 | 0x50 | R | 0 | Masked interrupt status for 64-bit mode |
| Table 18-20 | 0x54 | R/W | 0 | Timer dual 32-bit or 64-bit |