20.3.3 Timing Diagrams

The following figures show the timing of reset signals for reset sequences initiated by the assertion of POWER_ON_RESET_N, FIC_2_APB_M_PRESET_N, EXT_RESET_IN_N, and USER_FAB_RESET_IN_N signals.

Figure 20-25. Timing for Reset Signals Initiated by the Assertion of POWER_N_RESET_N

Figure 20-26. Timing for Reset Signals Initiated by the Assertion of FIC_2_APB_M_PRESET_N

Figure 20-27. Timing for Reset Signals Initiated by the Assertion of EXT_RESET_IN_N

Figure 20-28. Timing for Reset Signals Initiated by the Assertion of USER_FAB_RESET_IN_N

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