20.1.2 Power-Up to Functional Time Sequence
The following figure shows the power-up to functional time sequence diagram.
The following are the power-up to functional sequence:
- Supply Ramp (VDD, VPP, VDDI, and VDDAPLL): There is no specific power-up or power-down sequencing requirement for SmartFusion 2 devices. The I/O banks can be brought up in any order, before or after the core voltage. However, the device is only functional if all I/O bank supplies are powered up. All mandatory I/O bank supplies must be powered up. For all the devices, some of the bank supplies (VDDIx) must always be powered, even if associated bank I/Os are in unused condition. For the list of mandatory I/O bank supplies, refer to Table 2 and Table 3 in the SmartFusion2 and IGLOO2 Board Design Guidelines Application Note.
- On power-up, the POR generator block asserts the PO_RESET_N signal, which is not accessible for users.
- The 1 MHz RC oscillator is turned on, which provides the clock to the programmable delay counter. When the counter reaches its maximum value, the PO_RESET_N signal is de-asserted.
- The 1 MHz RC oscillator is gated off, and the 50 MHz RC oscillator is enabled and the System Controller starts operating at 50 MHz clock.
- FPGA fabric (LSRAM, uSRAM, and MATH), FDDR, and SerDes are turned on.
- Input buffer is enabled.
- POWER_ON_RESET_N signal (generated from the PO_RESET_N signal) is released. This signal can be used in the design as a reset for the FPGA fabric logic.
- Fabric PLL (Fabric CCC) Lock is asserted.
- MSS reset (SC_MSS_RESET_N) is released.
- MPLL (MSS CCC) Lock is asserted.
- MSS to Fabric Reset (MSS_RESET_N_M2F) is released.
- Output buffer is enabled.
The Reset Controller Configurator in the MSS Configurator enables the user to expose the MSS_RESET_N_M2F signal to the fabric. Refer to 20.4 How to Use the Reset Controller for more information. In order to simplify the task of initializing a user design in SmartFusion 2 devices, Microchip provides a CoreResetP soft Reset Controller IP. The CoreResetP handles the sequencing of reset signals in SmartFusion 2 devices. The CoreResetP generates a fabric reset signal whenever POWER_ON_RESET_N or MSS_RESET_N_M2F is asserted. It is available in the Libero SoC IP catalog. For more information, see 20.3 CoreResetP Soft Reset Controller.