20.1.1 Power-On Reset Generation Sequence

The following figure shows the conceptual block diagram of Power-on Reset generation. The POR generator block in System Controller generates a Power-on Reset signal, PO_RESET_N.

Figure 20-2. Conceptual Block Diagram of Power-On Reset Generation

Figure 20-5 shows the power-up to functional time sequence diagram. On power-up, the VDD and VPP monitor blocks in the POR generator block assert a Power-on Reset signal, PO_RESET_N. If the VDD and VPP supplies reach their threshold point (VDD ~ 0.9V and VPP ~ 0.9V), the 1 MHz RC Oscillator is turned-on, which provides the clock to the programmable delay counter. The delay can be configured to 50 µs, 1 ms, 10 ms, or 100 ms in the New Project window (Device Settings) while creating the Libero SoC project, as shown in the following figure. You can also access and change this setting after the project has been created from the Project Settings window (Project > Project Settings…). The delay setting (Power on Reset Delay) gets implemented in the design while generating bitstream.

Figure 20-3. Power on Reset Delay Configuration

The delay counter is used to generate the power supply rise time. All power supplies must be stable within the configured Power on Reset Delay. When the counter reaches its maximum value, the PO_RESET_N signal is de-asserted. Upon de-assertion of the PO_RESET_N signal, the 1 MHz RC oscillator is gated off and the 50 MHz RC oscillator is enabled, and the System Controller starts operating at 50 MHz clock. Then the System Controller starts the initialization sequence of I/O banks, MSS, and FPGA Fabric Subsystem.

The POWER_ON_RESET_N signal is generated from the PO_RESET_N signal and can be used in the user design as a reset for the FPGA fabric logic. It is an active-low output signal. It is made available by instantiating the SYSRESET macro from the Libero SoC IP catalog in SmartDesign or by instantiating the SYSRESET macro directly in the HDL file. The following figure shows a block symbol of the SYSRESET macro that exposes the POWER_ON_RESET_N signal.

Figure 20-4. SYSRESET Macro

POWER_ON_RESET_N asserts on the following events:

  • Power-up event
  • Assertion of DEVRST_N
  • Completion of programming
  • Completion of zeroization

A dedicated input-only reset pad (DEVRST_N) is present on all the SmartFusion 2 devices, which causes assertion to the PO_RESET_N signal. If an external reset circuit is connected to the DEVRST_N pin, it increases the power-up to functional time due to the delays that the external reset device does add.

DEVRST_N is an asynchronous RESET pin and must be asserted only when the device is unresponsive due to some unforeseen circumstances. It is not recommended to assert the DEVRST_N pin during programming operation, which might cause severe consequences, including corrupting the device configuration. For more details on DEVRST_N timing information, refer to the IGLOO2 and SmartFusion 2 Datasheet.

Asserting DEVRST_N does not enable the delay counter (Power on Reset Delay) in the POR circuitry.

The delay counter is operational only at power-up. When DEVRST_N is low, all user I/Os are fully tri-stated. Although the JTAG I/Os are still enabled, they cannot be used as the TAP controller is in reset. The SYSRESET macro is not required to be instantiated to enable the DEVRST_N pin in the user design. DEVRST_N is a dedicated input-only reset pad available on all the SmartFusion 2 devices.