1.2 Functional Description

The following figure shows the Cortex-M3 processor, core peripherals, and debug subsystem implementations used in SmartFusion 2.

Figure 1-1. Cortex-M3 Processor R2P1 Block Diagram as Implemented in the SmartFusion 2 SoC FPGA

The following topics are covered in detail in the sub-sections:

  • Cortex-M3 Processor NVIC
  • Cortex-M3 Processor SysTick Timer
  • Cortex-M3 Processor Debug Subsystem
  • Data Watch Point (DWP) and Trace
  • Instrumentation Trace Macrocell
  • Embedded Trace Macrocell
    Important: The Cortex-M3 operating frequency is dependent on device speed grade (up to 166 MHz). See the SmartFusion 2 Specifications-MSS Clock Frequency section from IGLOO 2 FPGA and SmartFusion 2 SoC FPGA Datasheet for more information.