1.1 Features

The Arm Cortex-M3 processor supports the following features:

  • A 32-bit processor core with low gate count and low latency interrupt processing
  • A RISC processor, with 3-stage pipeline Harvard architecture, pipeline core incorporating branch speculation, single cycle multiplication, and hardware division, giving a Dhrystone benchmark of 1.25 DMIPS/MHz.
  • A Nested Vectored Interrupt Controller (NVIC) that closely integrates with the processor core to achieve low latency interrupt processing.
  • A memory protection unit (MPU) is included. This facilitates the protected memory regions creation and setting access rights for the protected regions.
  • A Cortex-M3 processor, which is configured for SmartFusion 2 MSS, and uses only little-endian.
  • An auxiliary control register is included
  • Multiple high-performance bus interfaces that are connected through an advanced 
high-performance bus (AHB)
  • A debug solution with the optional ability to:
    • Implement breakpoints and code patches
    • Implement watchpoints, tracing, and system profiling
    • Support print style debugging
    • Bridge to a trace port analyzer

Manufacturers of the Cortex-M3 processor integrated circuits are permitted some latitude in configuring a particular implementation of the Cortex-M3 processor delivered by Arm. The following features are implementation specifics in the SmartFusion 2 device:

  • MPU: This helps in creating protected and protected regions of memory
  • Flash patch break point (FPB)
  • Data watchpoint and trace (DWT) unit
  • Instrumental trace macrocell (ITM)
  • Embedded trace macrocell (ETM)
  • Power-mode saving:
    • HCLK is gated off when in SLEEPING or SLEEPDEEP mode

      SLEEPING and SLEEPDEEP signals are available at the FPGA fabric interface sleep mode extension handshake signals are available at the FPGA fabric interface.

  • Not all registers in the register bank are reset
  • Endianness: little endian only
  • Auxiliary control register is included
  • Wake-up interrupt controller (WIC) is not included

For more details of these configurations and optional features, see 2 Cortex-M3 Processor (Reference Material).