1.3 Cortex-M3 Processor NVIC
The Cortex-M3 processor contains an NVIC, which is responsible for:
- Facilitating low-latency exception and interrupt handling
- Controlling power management
The following table lists the 11 exceptions that NVIC supports. The NVIC also supports up to 83 dynamically re-prioritizable external interrupts, each with up to 16 levels of priority (see Table 1-2). The NVIC maintains knowledge of stacked (nested) interrupts to enable tail-chaining of interrupts. In MSS, the NVIC is configured to have 16 levels of priority (4 msb in BASEPRI register) are implemented, so BASEPRI register [7-4] are used for the priority setting and [3-0] are read as zeros.
The following table lists exceptions. The detailed description of these exceptions can be found in the ARM Cortex-M3 Technical Reference Manual.
| Cortex-M3 Exceptions | Position in Interrupt Vector Table | Priority | Description |
|---|---|---|---|
| Reset | 1 (zero position is stack pointer) | –3 | Invoked on power-up and reset |
| Non-maskable exception | 2 | –2 | Non-maskable interrupt (NMI)—watchdog timeout interrupt |
| HardFault | 3 | –1 | Hard fault interrupt: all fault conditions if the corresponding fault handler is not enabled |
| Memory management exception | 4 | Configurable | Memory management interrupt: memory management fault; MPU violation or access to illegal locations. |
| Bus fault exception | 5 | Configurable | Bus fault interrupt: bus error; occurs when the AHB interface receives an error response from a bus slave (also called prefetch abort if it is an instruction fetch or data abort if it is a data access). |
| UsageFault | 6 | Configurable | Usage fault interrupt: exceptions resulting from a program error or trying to access a coprocessor (the Cortex-M3 does not support a coprocessor). |
| SVCall | 11 | Configurable | Supervisory call interrupt |
| Debug monitor | 12 | Configurable | Debug monitor interrupt: breakpoints, watchpoints, or external debug requests |
| PendSV | 14 | Configurable | Pend supervisory interrupt |
| SysTick | 15 | Configurable | System tick timer interrupt |
The interrupt sources listed in the following table are connected to the NVIC of the Cortex-M3 processor in the MSS.
| Cortex-M3 Interrupt | Signal | Source | Description |
|---|---|---|---|
| INTNMI | WDOGTIMEOUTINT | WATCHDOG | This interrupt is asserted (if enabled) if the counter reaches zero and interrupt rather than reset generation has been selected on counter timeout. |
| INTISR[0] | WDOGWAKEUPINT | WATCHDOG | This interrupt is asserted (if enabled) on crossing the WDOGMVRP level when the SLEEPING input is asserted. |
| INTISR[1] | RTC_WAKEUP_INTR | RTC | RTC match/wake up interrupt from RTC block |
| INTISR[2] | SPIINT0 | SPI_0 | Interrupt from SPI 0 |
| INTISR[3] | SPIINT1 | SPI_1 | Interrupt from SPI 1 |
| INTISR[4] | I2C_INT0 | I2C_0 | Interrupt from I2C 0 |
| INTISR[5] | I2C_SMBALERT0 | I2C_0 | Interrupt from I2C 0 |
| INTISR[6] | I2C_SMBSUS0 | I2C_0 | Interrupt from I2C 0 |
| INTISR[7] | I2C_INT1 | I2C_1 | Interrupt from I2C 1 |
| INTISR[8] | I2C_SMBALERT1 | I2C_1 | Interrupt from I2C 1 |
| INTISR[9] | I2C_SMBSUS1 | I2C_1 | Interrupt from I2C 1 |
| INTISR[10] | MMUART0_INTR | MMUART_0 | Interrupt from MMUART 0 |
| INTISR[11] | MMUART1_INTR | MMUART_1 | Interrupt from MMUART 1 |
| INTISR[12] | MAC_INT | MAC | Interrupt from Ethernet MAC |
| INTISR[13] | PDMAINTERRUPT | PDMA | Interrupt from peripheral DMA block |
| INTISR[14] | TIMER1_INTR | TIMER | Timer1 interrupt |
| INTISR[15] | TIMER2_INTR | TIMER | Timer2 interrupt |
| INTISR[16] | CAN_INTR | CAN | Interrupt from CAN |
| INTISR[17] | ENVM_INT0 | ENVMTOAHB0 | Asserted on an eNVM_0 basis at the completion of PROGRAM, ECC ERROR, etc. |
| INTISR[18] | ENVM_INT1 | ENVMTOAHB1 | Asserted on an eNVM_1 basis at the completion of PROGRAM, ECC ERROR, etc. |
| INTISR[19] | COMM_BLK_INTR | COMBLK | Communication block interrupt |
| INTISR[20] | USB_MC_INT | USB | CPU interrupts |
| INTISR[21] | USB_DMA_INT | USB | Core’s DMA engine performs data transfer between endpoint memories and system memory via AHB master port. DMA controller-interrupt. |
| INTISR[22] | MSSDDR_PLL_LOCK_INT | SYSREG | Interrupt indicating that MSSDDR PLL has achieved lock. |
| INTISR[23] | MSSDDR_PLL_LOCKLOST_INT | SYSREG | Interrupt indicating that MSSDDR PLL has lost lock. |
| INTISR[24] | SW_ERRORINTERRUPT | SYSREG | If set, it indicates to the Cortex-M3
processor that: – One of the masters of the switch attempted an access that resulted in either an error termination by the slave (or possibly the switch itself) or – Was decoded as an access to unimplemented address space or o. If the master attempted an access while disabled or – In the case of the fabric master, attempted to access the protected region of memory space This signal is set by ORing the fields of SW_ERRORSTATUS. It is cleared by writing 1 to the SW_CLEARSTATUS bit. |
| INTISR[25] | CACHE_ERRINTR | SYSREG | If asserted, indicates that the interrupt is coming from CACHE. This interrupt is generated in the SysReg by ORing of the various interrupts from the CACHE block: CC_HRESPERRINT0, CC_HRESPERRINT1, CC_HRESPERRINT2, CC_HRESPERRINT3. |
| INTISR[26] | DDRB_INTR | SYSREG | If asserted, indicates that the
interrupt is coming from DDRBRDIGE module.
Interrupts from MSS DDR
Bridge module: DDRB_ERROR and DDRB_LOCKTIMEOUT. These interrupts are ORed in the SysReg and fed to the Cortex-M3 processor. |
| INTISR[27] | HPD_XFR_CMP_INT | HPDMA | It is asserted when any HPDMA completes a descriptor transfer. Once asserted, it remains asserted until cleared by means of writing 1 to the bit in the control register of the Descriptor-N (0, 1, 2, 3). If HPDMA completes more than one descriptor transfers before the interrupt is serviced then this bit remains asserted until all the descriptors have had Clr_D<N>_Xfr_cmp_int written to 1. |
| INTISR[28] | HPD_XFR_ERR_INT | HPDMA | It is asserted when any HPDMA completes a descriptor transfer with error. Once asserted, it remains asserted until cleared by means of writing 1 to the bit in the control register of the Descriptor-N (0, 1, 2, 3). If HPDMA completes more than one descriptor with errors before the interrupt is serviced then this bit remains asserted until all the descriptors have had Clr_D<N>_Xfr_err_int written to 1. |
| INTISR[29] | ECCINTR | SYSREG | It is asserted when an ECC error has been detected in ESRAM0, ESRAM1, MAC, CAN, MDDR, and USB. This is generated by ORing ECC interrupts from these modules. |
| INTISR[30] | MDDR_IO_CALIB_INT | SYSREG | The interrupt is generated when MDDR
calibration is finished. For the calibration after reset, this would be
followed by locking the codes directly. However, for in-between runs during functional DDR operation, the assertion of interrupt does not guarantee lock as the state machine would wait for the ideal time (DRAM self-refresh) for locking. This can be used by the firmware to insert an ideal time, and provides an indication of availability of locked codes. |
| INTISR[31] | FAB_PLL_LOCK_INT | SYSREG | Interrupt indicating that MSSDDR PLL has achieved lock |
| INTISR[32] | FAB_PLL_LOCKLOST_INT | SYSREG | Interrupt indicating that MSSDDR PLL has lost lock |
| INTISR[33] | FIC64_INT | SYSREG | This interrupt will be generated by
FIC64 when one of the following conditions is true: Write error for HPDMA or switch WCBs (from DDR_AXI_INTF) Simultaneous read and write accesses by HPDMA and switch for same address Lock time out condition |
| INTISR[34] | F2H_INTERRUPT[0] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[35] | F2H_INTERRUPT[1] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[36] | F2H_INTERRUPT[2] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[37] | F2H_INTERRUPT[3] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[38] | F2H_INTERRUPT[4] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[39] | F2H_INTERRUPT[5] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[40] | F2H_INTERRUPT[6] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[41] | F2H_INTERRUPT[7] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[42] | F2H_INTERRUPT[8] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[43] | F2H_INTERRUPT[9] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[44] | F2H_INTERRUPT[10] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[45] | F2H_INTERRUPT[11] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[46] | F2H_INTERRUPT[12] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[47] | F2H_INTERRUPT[13] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[48] | F2H_INTERRUPT[14] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[49] | F2H_INTERRUPT[15] | FPGA fabric | Interrupt from the FPGA fabric |
| INTISR[50] | GPIO_INT[0] | GPIO | Interrupt from GPIO |
| INTISR[51] | GPIO_INT[1] | GPIO | Interrupt from GPIO |
| INTISR[52] | GPIO_INT[2] | GPIO | Interrupt from GPIO |
| INTISR[53] | GPIO_INT[3] | GPIO | Interrupt from GPIO |
| INTISR[54] | GPIO_INT[4] | GPIO | Interrupt from GPIO |
| INTISR[55] | GPIO_INT[5] | GPIO | Interrupt from GPIO |
| INTISR[56] | GPIO_INT[6] | GPIO | Interrupt from GPIO |
| INTISR[57] | GPIO_INT[7] | GPIO | Interrupt from GPIO |
| INTISR[58] | GPIO_INT[8] | GPIO | Interrupt from GPIO |
| INTISR[59] | GPIO_INT[9] | GPIO | Interrupt from GPIO |
| INTISR[60] | GPIO_INT[10] | GPIO | Interrupt from GPIO |
| INTISR[61] | GPIO_INT[11] | GPIO | Interrupt from GPIO |
| INTISR[62] | GPIO_INT[12] | GPIO | Interrupt from GPIO |
| INTISR[63] | GPIO_INT[13] | GPIO | Interrupt from GPIO |
| INTISR[64] | GPIO_INT[14] | GPIO | Interrupt from GPIO |
| INTISR[65] | GPIO_INT[15] | GPIO | Interrupt from GPIO |
| INTISR[66] | GPIO_INT[16] | GPIO | Interrupt from GPIO |
| INTISR[67] | GPIO_INT[17] | GPIO | Interrupt from GPIO |
| INTISR[68] | GPIO_INT[18] | GPIO | Interrupt from GPIO |
| INTISR[69] | GPIO_INT[19] | GPIO | Interrupt from GPIO |
| INTISR[70] | GPIO_INT[20] | GPIO | Interrupt from GPIO |
| INTISR[71] | GPIO_INT[21] | GPIO | Interrupt from GPIO |
| INTISR[72] | GPIO_INT[22] | GPIO | Interrupt from GPIO |
| INTISR[73] | GPIO_INT[23] | GPIO | Interrupt from GPIO |
| INTISR[74] | GPIO_INT[24] | GPIO | Interrupt from GPIO |
| INTISR[75] | GPIO_INT[25] | GPIO | Interrupt from GPIO |
| INTISR[76] | GPIO_INT[26] | GPIO | Interrupt from GPIO |
| INTISR[77] | GPIO_INT[27] | GPIO | Interrupt from GPIO |
| INTISR[78] | GPIO_INT[28] | GPIO | Interrupt from GPIO |
| INTISR[79] | GPIO_INT[29] | GPIO | Interrupt from GPIO |
| INTISR[80] | GPIO_INT[30] | GPIO | Interrupt from GPIO |
| INTISR[81] | GPIO_INT[31] | GPIO | Interrupt from GPIO |