1.6 Cortex-M3 Processor Port Descriptions

The following table lists all the ports related to the Cortex-M3 subsystem, their direction, and a description of the ports.

Table 1-4. Port Details of the Cortex-M3-Subsystem
Port NameDirectionPadDescription
RXEVInNoCauses the Cortex-M3 to wake up from a wait for event (WFE) instruction. The event input, RXEV, is registered even when not waiting for an event, and so affects the next WFE.
TXEVOutNoEvent transmitted as a result of a Cortex-M3 SEV (send event) instruction. This is a single-cycle pulse equal to 1 M3_CLK period.
SLEEPOutNoSignal is asserted when the Cortex-M3 processor is in sleep now or sleep-on-exit mode, and indicates that the clock to the processor can be stopped.
DEEPSLEEPOutNoSignal is asserted when the Cortex-M3 processor is in sleep now or sleep-on-exit mode when the SLEEPDEEP bit of the system control register is set.
SLEEPHOLDREQnInNoRequest to extend Cortex-M3 processor sleep state. Signal is asserted when SLEEPING signal is High.
SLEEPHOLDACKnOutNoSignal is asserted to confirm the Cortex-M3 processor sleep state extension request.
TRACECLKOutNoTRACETRACEDATA changes on both the edges of TRACECLK.
TRACEDATA[3:0]OutNoOutput data for clocked modes.