15.2 MSS GPIO Functional Description

The following figure shows the internal architecture of the MSS GPIO block. GPIOs and MSS peripherals, such as MMUART, SPI, and I2C, can be routed to MSIO pads or to the Field Programmable Gate Array (FPGA) fabric through I/O mutliplexers (MUXes), as shown in the following figure.

Figure 15-2. GPIO, IOMUX, and MSIO

The MSS GPIO block contains the following:

  • 32-bit input register (GPIO_IN), which holds the input values
  • 32-bit output register (GPIO_OUT), which holds the output values
  • 32-bit interrupt register (GPIO_IRQ), which holds the interrupt state
  • 32 configuration registers (GPIO_X_CFG), one register for each GPIO

When a GPIO is configured in Input mode, the GPIO input is passed through a 2 flip-flop synchronizer and latched into the GPIO_IN register. The GPIO_IN register value is read through the APB bus and is accessible to the Cortex-M3 processor or fabric master. The input to the GPIO can be from the fabric or MSIO pad.

The GPIO_IN register output can also be used as an interrupt to the Cortex-M3 processor. This can be configured as an edge-triggered (on rising edge, falling edge, or both edges) or as a level sensitive (active-low or active-high) interrupt. The interrupt is latched in the GPIO_IRQ register and is accessible through the APB bus, as shown in Table 15-2.

In Edge-Sensitive mode, GPIO_IRQ register is cleared either by disabling the interrupt or writing a logic 1 through the APB interface. If an edge and GPIO_IRQ clearing through the APB occurs simultaneously, the edge has higher priority.

Table 15-2 maps the GPIO input to the Nested Vectored Interrupt Controller (NVIC) interrupt number in the Cortex-M3 processor. The interrupt input to the GPIO can be from the fabric or MSIO pad.

When the GPIO is configured in an Output mode, the output value can be configured using the APB bus and is accessible to the Cortex-M3 processor or fabric master. The GPIO output can be available to the MSIO pad, fabric, or the FPGA and MSIO pads.

For configuring GPIO in Input, Output, and Bi-directional modes, see the bit definitions in Table 15-1.

Figure 15-3. MSS GPIO Block Diagram