15.2.1 MSS GPIO Configuration Registers (GPIO_X_CFG)
In the MSS GPIO block, each GPIO has a 32-bit configuration register. The configuration register allows selection of the GPIO in Input, Output, or Bi-directional mode. A GPIO can also be used as an interrupt when it is configured in Bi-directional mode. The offset address of MSS GPIO block configuration registers is given in Table 15-4. The following figure shows the detailed configuration register bit definitions.
The following table provides bit definitions for the GPIO configuration registers.
| Bit Number | Name | Type | Reset Value | Description |
|---|---|---|---|---|
| GPIO_X_CFG[31:8] | Reserved | R/W | 0h000000 | Reserved |
| GPIO_X_CFG[7:5] | TYPES_INT_I | R/W | 0b000 | Input interrupt type configuration See Figure 15-4 for Bit definitions. |
| GPIO_X_CFG[4] | Reserved | R/W | 0b0 | Reserved |
| GPIO_X_CFG[3] | EN_INT_i | R/W | 0b0 | 0: Interrupt disabled 1: Interrupt enabled |
| GPIO_X_CFG[2] | GPIO_i_OE | R/W | 0b0 | 0: Disable output buffer 1: Enable output buffer |
| GPIO_X_CFG[1] | EN_IN_i | R/W | 0b0 | 0: Input register disabled 1: Input register enabled |
| GPIO_X_CFG[0] | EN_OUT_i | R/W | 0b0 | 0: Output register disabled 1: Output register enabled |
| Cortex-M3 Processor Interrupt | Signal | Source | Description |
|---|---|---|---|
| INTISR[50] | GPIO_INT[0] | GPIO_0 | Interrupt from GPIO_0 |
| INTISR[51] | GPIO_INT[1] | GPIO_1 | Interrupt from GPIO_1 |
| INTISR[52] | GPIO_INT[2] | GPIO_2 | Interrupt from GPIO_2 |
| INTISR[53] | GPIO_INT[3] | GPIO_3 | Interrupt from GPIO_3 |
| INTISR[54] | GPIO_INT[4] | GPIO_4 | Interrupt from GPIO_4 |
| INTISR[55] | GPIO_INT[5] | GPIO_5 | Interrupt from GPIO_5 |
| INTISR[56] | GPIO_INT[6] | GPIO_6 | Interrupt from GPIO_6 |
| INTISR[57] | GPIO_INT[7] | GPIO_7 | Interrupt from GPIO_7 |
| INTISR[58] | GPIO_INT[8] | GPIO_8 | Interrupt from GPIO_8 |
| INTISR[59] | GPIO_INT[9] | GPIO_9 | Interrupt from GPIO_9 |
| INTISR[60] | GPIO_INT[10] | GPIO_10 | Interrupt from GPIO_10 |
| INTISR[61] | GPIO_INT[11] | GPIO_11 | Interrupt from GPIO_11 |
| INTISR[62] | GPIO_INT[12] | GPIO_12 | Interrupt from GPIO_12 |
| INTISR[63] | GPIO_INT[13] | GPIO_13 | Interrupt from GPIO_13 |
| INTISR[64] | GPIO_INT[14] | GPIO_14 | Interrupt from GPIO_14 |
| INTISR[65] | GPIO_INT[15] | GPIO_15 | Interrupt from GPIO_15 |
| INTISR[66] | GPIO_INT[16] | GPIO_16 | Interrupt from GPIO_16 |
| INTISR[67] | GPIO_INT[17] | GPIO_17 | Interrupt from GPIO_17 |
| INTISR[68] | GPIO_INT[18] | GPIO_18 | Interrupt from GPIO_18 |
| INTISR[69] | GPIO_INT[19] | GPIO_19 | Interrupt from GPIO_19 |
| INTISR[70] | GPIO_INT[20] | GPIO_20 | Interrupt from GPIO_20 |
| INTISR[71] | GPIO_INT[21] | GPIO_21 | Interrupt from GPIO_21 |
| INTISR[72] | GPIO_INT[22] | GPIO_22 | Interrupt from GPIO_22 |
| INTISR[73] | GPIO_INT[23] | GPIO_23 | Interrupt from GPIO_23 |
| INTISR[74] | GPIO_INT[24] | GPIO_24 | Interrupt from GPIO_24 |
| INTISR[75] | GPIO_INT[25] | GPIO_25 | Interrupt from GPIO_25 |
| INTISR[76] | GPIO_INT[26] | GPIO_26 | Interrupt from GPIO_26 |
| INTISR[77] | GPIO_INT[27] | GPIO_27 | Interrupt from GPIO_27 |
| INTISR[78] | GPIO_INT[28] | GPIO_28 | Interrupt from GPIO_28 |
| INTISR[79] | GPIO_INT[29] | GPIO_29 | Interrupt from GPIO_29 |
| INTISR[80] | GPIO_INT[30] | GPIO_30 | Interrupt from GPIO_30 |
| INTISR[81] | GPIO_INT[31] | GPIO_31 | Interrupt from GPIO_31 |