19.4.1 Watchdog Timer Configuration Register Bit Definitions

The watchdog timer registers are described in detail in the following tables. 

Table 19-4. WDOGVALUE
Bit NumberNameReset ValueDescription
[31:0]WDOGVALUEWDOGLOADThis register contains the current value of the counter in the watchdog timer. This register is reset with the value in the WDOGLOAD system register.

 

Table 19-5. WDOGLOAD
Bit NumberNameReset ValueDescription
[31:0]WDOGLOAD[31:6]WDOGLOADThis register contains the upper 26 bits load value for the counter in the watchdog timer. This will be updated by the WDOGLOAD[25:0] bits of the system registers. The least significant bits of the register always have the value of 0x3F.
Table 19-6. WDOGMVRP
Bit NumberNameReset ValueDescription
[31:0]WDOGMVRPWDOGMVRPThis register contains the maximum value for which refreshing is permitted.

If the watchdog timer is refreshed (by writing to the WDOGREFRESH register) while the counter value is greater than the value in the WDOGMVRP, then a reset/interrupt is generated. This read only register is loaded with the user flash bit value written in the WDOGMVRP[31:0] system register.

Table 19-7. WDOGREFRESH
Bit NumberNameReset ValueDescription
[31:0]WDOGREFRESHN/AThis is a write only register which reads as zero. Writing the value 0xAC15DE42 to this register causes the counter to be refreshed with the value in the Table 19-5 register.

If this register is written to, while the current value of the counter is greater than the value in the Table 19-6 register, the counter is refreshed and a reset or timeout interrupt is generated (depending on the MODE bit of the WDOGCONTROL). While the counter value is greater than the Table 19-6, there is effectively a time window in which it is forbidden to refresh the watchdog timer.

When the counter is in between the Table 19-6 level and 0, the watchdog timer is in a time window where it is permitted for it to be refreshed.

It is possible to avoid having the forbidden and permitted time windows for refreshing the watchdog timer by setting the value of the Table 19-6 to a value greater than that stored in the Table 19-5.

Table 19-8. WDOGENABLE
Bit NumberNameReset ValueDescription
[31:1]Reserved0x0Reserved
0ENABLEWDOGENABLEEnable bit for watchdog timer.

This bit holds the value of the USER FLASH bit written in the WDOGENABLE bit of the WDOG_CR system register.

Table 19-9. WDOGCONTROL
Bit NumberNameReset ValueDescription
[31:3]Reserved0To provide compatibility to the future products, the value of a reserved bit should be preserved across a read-modify-write operation.
2MODEWDOGMODEOperation mode for the watchdog timer.

0: reset is generated if counter reaches zero.

1: interrupt is generated if counter reaches zero.

This read only register holds the value of user flash bit written in the WDOGMODE bit of the WDOG_CR system register.

1WAKEUPINTEN00: The WDOGWAKEUPINT interrupt generation is disabled.

1: The WDOGWAKEUPINT interrupt generation is enabled.

0TIMEOUTINTEN00: The WDOGTIMEOUTINT interrupt generation is disabled.

1: The WDOGTIMEOUTINT interrupt generation is enabled.

Table 19-10. WDOGSTATUS
Bit NumberNameReset ValueDescription
[31:1]Reserved0To provide the compatibility to the future products, the value of a reserved bit should be preserved across a read-modify-write operation
0REFRESHSTATUS0Refresh status

0: The counter is in forbidden window, refresh should not be initiated.

1: The counter in is permitted window, refresh is allowed.

 

 

Table 19-11. WDOGRIS
Bit NumberNameReset ValueDescription
[31:2]Reserved0To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
1WAKEUPRS0Raw status of wakeup interrupt.

Writing '1' to this bit clears the bit. Writing '0' has no effect.

0TIMEOUTRS0Raw status of counter timeout interrupts.

Writing '1' to this bit clears the bit. Writing '0' has no effect.