| DMAREADY_FIC_0 |
Input |
High |
Main Fabric Interface: Each of these bits corresponds to a ready signal from a soft peripheral in the FPGA fabric. If the channel is configured for peripheral DMA and the direction is from the soft peripheral to memory, then this signal indicates that data is available within the soft peripheral to be read out. If the channel is configured for peripheral DMA and the direction is to the soft peripheral from memory, then this signal indicates that there is space within the soft peripheral for data to be written to it. This signal is asserted high. |
| DMAREADY_FIC_1 |
Input |
High |
Second Fabric Interface: Each of these bits corresponds to a ready signal from a soft peripheral in the FPGA fabric. If the channel is configured for peripheral DMA and the direction is from the soft peripheral to memory, then this signal indicates that data is available within the soft peripheral to be read out. If the channel is configured for peripheral DMA and the direction is to the soft peripheral from memory, then this signal indicates that there is space within the soft peripheral for data to be written to it. This signal is asserted high. |
