8.4 PDMA Register Map
The following table summarizes each of the registers covered by this document. The base address is 0x40003000.
| Register Name | Address Offset | Register Type | Reset Value | Description |
|---|---|---|---|---|
| RATIO_HIGH_LOW Register Bit Definition (Table 8-5) | 0x00 | R/W | 0 | Ratio of high priority transfers versus low priority transfers. |
| BUFFER_STATUS Register Bit Definition (Table 8-6) | 0x04 | R | 0 | Indicates when buffers have drained. |
| CHANNEL_x_CONTROL Register Bit Definition (Table 8-7 (X=0)) | 0x20 | R/W | 0 | Channel 0 Control register |
| CHANNEL_x_STATUS Register Bit Definition (Table 8-9 (X=0)) | 0x24 | R | 0 | Channel 0 Status register |
| CHANNEL_x_BUFFER_A_SRC_ADDR Register Bit Definition (Table 8-10 (x=0)) | 0x28 | R/W | 0 | Channel 0 buffer A source address |
| CHANNEL_x_BUFFER_A_DST_ADDR Register Bit Definition (Table 8-11 (x=0)) | 0x2C | R/W | 0 | Channel 0 buffer A destination address |
| CHANNEL_x_BUFFER_A_TRANSFER_COUNT Register Bit Definition (Table 8-12 (x=0)) | 0x30 | R/W | 0 | Channel 0 buffer A transfer count |
| CHANNEL_x_BUFFER_B_SRC_ADDR Register Bit Definition (Table 8-13 (x=0)) | 0x34 | R/W | 0 | Channel 0 buffer B source address |
| CHANNEL_x_BUFFER_B_DST_ADDR Register Bit Definition (Table 8-14 (x=0)) | 0x38 | R/W | 0 | Channel 0 buffer B destination address |
| CHANNEL_x_BUFFER_B_TRANSFER_COUNT Register Bit Definition (Table 8-15 (x=0)) | 0x3C | R/W | 0 | Channel 0 buffer B transfer count |
| CHANNEL_1_CONTROL | 0x40 | R/W | 0 | Channel 1 Control register |
| CHANNEL_1_STATUS | 0x44 | R | 0 | Channel 1 Status register |
| CHANNEL_1_BUFFER_A_SRC_ADDR | 0x48 | R/W | 0 | Channel 1 buffer A source address |
| CHANNEL_1_BUFFER_A_DST_ADDR | 0x4C | R/W | 0 | Channel 1 buffer A destination address |
| CHANNEL_1_BUFFER_A_TRANSFER_COUNT | 0x50 | R/W | 0 | Channel 1 buffer A transfer count |
| CHANNEL_1_BUFFER_B_SRC_ADDR | 0x54 | R/W | 0 | Channel 1 buffer B source address |
| CHANNEL_1_BUFFER_B_DST_ADDR | 0x58 | R/W | 0 | Channel 1 buffer B destination address |
| CHANNEL_1_BUFFER_B_TRANSFER_COUNT | 0x5C | R/W | 0 | Channel 1 buffer B transfer count |
| CHANNEL_2_CONTROL | 0x60 | R/W | 0 | Channel 2 Control register |
| CHANNEL_2_STATUS | 0x64 | R | 0 | Channel 2 Status register |
| CHANNEL_2_BUFFER_A_SRC_ADDR | 0x68 | R/W | 0 | Channel 2 buffer A source address |
| CHANNEL_2_BUFFER_A_DST_ADDR | 0x6C | R/W | 0 | Channel 2 buffer A destination address |
| CHANNEL_2_BUFFER_A_TRANSFER_COUNT | 0x70 | R/W | 0 | Channel 2 buffer A transfer count |
| CHANNEL_2_BUFFER_B_SRC_ADDR | 0x74 | R/W | 0 | Channel 2 buffer B source address |
| CHANNEL_2_BUFFER_B_DST_ADDR | 0x78 | R/W | 0 | Channel 2 buffer B destination address |
| CHANNEL_2_BUFFER_B_TRANSFER_COUNT | 0x7C | R/W | 0 | Channel 2 buffer B transfer count |
| CHANNEL_3_CONTROL | 0x80 | R/W | 0 | Channel 3 Control register |
| CHANNEL_3_STATUS | 0x84 | R | 0 | Channel 3 Status register |
| CHANNEL_3_BUFFER_A_SRC_ADDR | 0x88 | R/W | 0 | Channel 3 buffer A source address |
| CHANNEL_3_BUFFER_A_DST_ADDR | 0x8C | R/W | 0 | Channel 3 buffer A destination address |
| CHANNEL_3_BUFFER_A_TRANSFER_COUNT | 0x90 | R/W | 0 | Channel 3 buffer A transfer count |
| CHANNEL_3_BUFFER_B_SRC_ADDR | 0x94 | R/W | 0 | Channel 3 buffer B source address |
| CHANNEL_3_BUFFER_B_DST_ADDR | 0x98 | R/W | 0 | Channel 3 buffer B destination address |
| CHANNEL_3_BUFFER_B_TRANSFER_COUNT | 0x9C | R/W | 0 | Channel 3 buffer B transfer count |
| CHANNEL_4_CONTROL | 0xA0 | R/W | 0 | Channel 4 Control register |
| CHANNEL_4_STATUS | 0xA4 | R | 0 | Channel 4 Status register |
| CHANNEL_4_BUFFER_A_SRC_ADDR | 0xA8 | R/W | 0 | Channel 4 buffer A source address |
| CHANNEL_4_BUFFER_A_DST_ADDR | 0xAC | R/W | 0 | Channel 4 buffer A destination address |
| CHANNEL_4_BUFFER_A_TRANSFER_COUNT | 0xB0 | R/W | 0 | Channel 4 buffer A transfer count |
| CHANNEL_4_BUFFER_B_SRC_ADDR | 0xB4 | R/W | 0 | Channel 4 buffer B source address |
| CHANNEL_4_BUFFER_B_DST_ADDR | 0xB8 | R/W | 0 | Channel 4 buffer B destination address |
| CHANNEL_4_BUFFER_B_TRANSFER_COUNT | 0xBC | R/W | 0 | Channel 4 buffer B transfer count |
| CHANNEL_5_CONTROL | 0xC0 | R/W | 0 | Channel 5 Control register |
| CHANNEL_5_STATUS | 0xC4 | R | 0 | Channel 5 Status register |
| CHANNEL_5_BUFFER_A_SRC_ADDR | 0xC8 | R/W | 0 | Channel 5 buffer A source address |
| CHANNEL_5_BUFFER_A_DST_ADDR | 0xCC | R/W | 0 | Channel 5 buffer A destination address |
| CHANNEL_5_BUFFER_A_TRANSFER_COUNT | 0xD0 | R/W | 0 | Channel 5 buffer A transfer count |
| CHANNEL_5_BUFFER_B_SRC_ADDR | 0xD4 | R/W | 0 | Channel 5 buffer B source address |
| CHANNEL_5_BUFFER_B_DST_ADDR | 0xD8 | R/W | 0 | Channel 5 buffer B destination address |
| CHANNEL_5_BUFFER_B_TRANSFER_COUNT | 0xDC | R/W | 0 | Channel 5 buffer B transfer count |
| CHANNEL_6_CONTROL | 0xE0 | R/W | 0 | Channel 6 Control register |
| CHANNEL_6_STATUS | 0xE4 | R | 0 | Channel 6 Status register |
| CHANNEL_6_BUFFER_A_SRC_ADDR | 0xE8 | R/W | 0 | Channel 6 buffer A source address |
| CHANNEL_6_BUFFER_A_DST_ADDR | 0xEC | R/W | 0 | Channel 6 buffer A destination address |
| CHANNEL_6_BUFFER_A_TRANSFER_COUNT | 0xF0 | R/W | 0 | Channel 6 buffer A transfer count |
| CHANNEL_6_BUFFER_B_SRC_ADDR | 0xF4 | R/W | 0 | Channel 6 buffer B source address |
| CHANNEL_6_BUFFER_B_DST_ADDR | 0xF8 | R/W | 0 | Channel 6 buffer B destination address |
| CHANNEL_6_BUFFER_B_TRANSFER_COUNT | 0xFC | R/W | 0 | Channel 6 buffer B transfer count |
| CHANNEL_7_CONTROL | 0x100 | R/W | 0 | Channel 7 Control register |
| CHANNEL_7_STATUS | 0x104 | R | 0 | Channel 7 Status register |
| CHANNEL_7_BUFFER_A_SRC_ADDR | 0x108 | R/W | 0 | Channel 7 buffer A source address |
| CHANNEL_7_BUFFER_A_DST_ADDR | 0x10C | R/W | 0 | Channel 7 buffer A destination address |
| CHANNEL_7_BUFFER_A_TRANSFER_COUNT | 0x110 | R/W | 0 | Channel 7 buffer A transfer count |
| CHANNEL_7_BUFFER_B_SRC_ADDR | 0x114 | R/W | 0 | Channel 7 buffer B source address |
| CHANNEL_7_BUFFER_B_DST_ADDR | 0x118 | R/W | 0 | Channel 7 buffer B destination address |
| CHANNEL_7_BUFFER_B_TRANSFER_COUNT | 0x11C | R/W | 0 | Channel 7 buffer B transfer count |