17.2.2 Port List
The following table lists the ports of the RTC and provides a short description for each.
| Port | MSB | LSB | Dir | Description |
|---|---|---|---|---|
| PCLK | in | APB interface clock. | ||
| PRESETN | in | Processor reset | ||
| PADDR | 6 | 0 | in | APB address. Registers are word aligned so A1:0 is not used. |
| PSEL | in | APB select signal | ||
| PENABLE | in | APB enable | ||
| PWRITE | in | APB write signal | ||
| PWDATA | 31 | 0 | in | APB write data bus |
| PREADY | out | APB ready signal; is always asserted | ||
| PRDATA | 31 | 0 | out | APB read data bus |
| RTC_MATCH | out | RTC match output (active-high) Synchronous to clk 32 k | ||
| RTC_WAKEUP | out | RTC wake up interrupt (active-high). Asserted Synchronous to clk 32 k, but deasserted on positive edge of PCLK | ||
| CLKRTC | in | Clock input for RTC counters | ||
| PORST_B | in | Power-on reset. It clears/preset all flip-flops including the calendar/prescaler counters (active-low) |