5.3 How to Use eSRAM

This section describes how to use eSRAM in the SmartFusion 2 devices. To configure the SmartFusion 2 device features and then build a complete system, use the System Builder graphical design wizard in the Libero SoC software.

The following figure shows the initial System Builder window where the required device features can be selected. For information on how to launch the System Builder wizard and a detailed information on how to use it, see SmartFusion2 System Builder User Guide.

Figure 5-3. System Builder Window

Any master (for example, Cortex-M3 processor, FPGA fabric master, HPDMA, or PDMA) connected to the AHB bus matrix can access the eSRAM blocks using the address range provided in Table 5-1 for read and write operations.

The following steps are used to configure Programmable Slave Maximum Latency for eSRAM_0 and eSRAM_1 blocks and eSRAM SECDED feature in the application using System Builder.

  1. Navigate to the Microcontroller tab in the System Builder window to configure Programmable Slave Maximum Latency for eSRAM_0 and eSRAM_1 blocks. The following figure shows the System Builder > Microcontroller tab. For more information on the Programmable Slave Maximum Latency configuration and remapping eSRAM to Cortex-M3 code space, click Help and select AHB Bus Matrix document, as shown in the following figure. See 
AC390: SmartFusion2 SoC FPGA – Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Note.

    Figure 5-4. System Builder - Microcontroller Tab

  2. Navigate to the SECDED tab in the System Builder window to configure SECDED options for eSRAM_0 and eSRAM_1. The following figure shows the SECDED tab. For more information on SECDED, click Help and select SECDED document. See 
DG0388: SmartFusion2 SoC FPGA Error Detection and Correction of eSRAM Memory Demo Guide.

    Figure 5-5. System Builder - SECDED Tab

    The SECDED feature can be enabled or disabled by selecting Enable EDAC for eSRAM_0 and eSRAM_1. The interrupts for 1-bit error or 2-bit error, or both 1-bit and 2-bit errors can be enabled.

  3. Navigate to the Security tab to select the read and write access permissions of eSRAM for different masters, as shown in the following figure. The read and write permission for different masters are available for data and design security enabled devices like M2S050TS only. For more information on configuring the security options, see SmartFusion2 MSS Security Configuration.

    Figure 5-6. System Builder - Security Tab
  4. Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs and click Finish to proceed with creating the MSS Subsystem.
  5. Do required Pin connections and Save the project. Click Generate Component to generate the SmartDesign in Libero.
  6. Double click Run PROGRAM Action in the Libero Design Flow window to program the SmartFusion 2 device.
Important: For information on how to access the eSRAM using FPGA fabric logic, see AC429: Accessing eNVM and eSRAM from the FPGA Fabric Logic Application Note.