5.4 SYSREG Control Registers

The registers listed in the following table control the behavior of the eSRAM. For more information on these registers, see Table 21-2. For a detailed description of each register and bit, see 21 System Register Block.

Table 5-5. SYSREG Control Registers
Register Name Register Type Flash Write Protect Reset Source Description
Table 5-6 (0x40038000) RW-P Register SYSRESET_N Controls address mapping of the eSRAMs.
Table 5-7
(0x40038004) RW-P Register SYSRESET_N Configuration of maximum latency for accessing eSRAM_0 and eSRAM_1 slaves. This register gets updated by Flash bit configuration set during device programming. This configuration can be done through the System Builder also using settings on the Microcontroller Tab.
Table 5-9
(0x40038080) RW-P Register SYSRESET_N Controls the pipeline present in the memory read path of eSRAM memory.
Table 5-10
(0x400380F0) RO N/A SYSRESET_N Represents 1-bit error count of eSRAM_0.
Table 5-11
(0x400380F4) RO N/A SYSRESET_N Represents 1-bit error count of eSRAM_1.
Table 5-12
(0x4003810C) RO N/A SYSRESET_N Address from eSRAM_0 on which 1-bit ECC error has occurred.
Table 5-13
(0x40038110) RO N/A SYSRESET_N Address from eSRAM_1 on which 1-bit ECC error has occurred.
Table 5-14
(0x40038124) RO-U N/A SYSRESET_N Read and Write security for Mirrored Master (MM) 0, 1, and 2 to eSRAM_0 and eSRAM_1.
Table 5-15(0x40038128) RO-U N/A SYSRESET_N Read and Write security for Mirrored Master (MM) 4, 5, and DDR_FIC to eSRAM_0 and eSRAM_1. This register gets updated by Flash bit configuration set during device programming. This configuration can be done through the System Builder using settings on the Security tab.
Table 5-16
(0x4003812C) RO-U N/A SYSRESET_N Read and Write security for Mirrored Master (MM) 3, 6, 7, and 8 to eSRAM_0 and eSRAM_1. This register gets updated by Flash bit configuration set during device programming. This configuration can be done through the System Builder using settings on the Security tab.
Table 5-17
(0x40038130) RO-U N/A SYSRESET_N Read and Write security for Mirrored Master (MM) 9 to eSRAM_0 and eSRAM_1. This register gets updated by Flash bit configuration set during device programming. This configuration can be done through the System Builder using settings on the Security tab.
Table 5-18
(0x40038190) SW1C N/A SYSRESET_N Status of 1-bit ECC error detection and correction (EDAC), 2-bit ECC error detection for eSRAM_0 and eSRAM_1. Individual register bits are set (1) when related input is asserted. Bits are individually cleared when corresponding register bit is written High.
Table 5-19
(0x400381A4) W1P N/A SYSRESET_N This is used to clear the 16-bit counter value in eSRAM_0 and eSRAM_1 corresponding to the count value of EDAC 1-bit and 2-bit errors.
Table 5-20
(0x40038078) RW-P Register SYSRESET_N Enable/disable of 1-bit error, 2-bit error status update for eSRAM_0 and eSRAM_1. This can be set by the System Builder using settings on the SECDED tab.
Table 5-21
(0x40038038) RW-P Register SYSRESET_N EDAC enable/disable and soft reset for eSRAM_0 and eSRAM_1. This can be set by the System Builder using settings on the SECDED tab.
Table 5-6. ESRAM_CR
Bit Number Name Reset Value Description
[31:2] Reserved 0 Reserved
1 SW_CC_ESRAM1FWREMAP 0 Defines the locations of eSRAM_0 and eSRAM_1, if eSRAM remap is enabled (if SW_CC_ESRAMFWREMAP is asserted). If SW_CC_ESRAMFWREMAP is 0, this bit has no meaning. If SW_CC_ESRAMFWREMAP is 1, this bit has the following definition:
  • 0: eSRAM_0 is located at address 0x00000000 in the ICODE/DCODE space of Cortex®-M3 processor and eSRAM_1 is located just above eSRAM_0 (adjacent to it).
  • 1: eSRAM_1 is located at address 0x00000000 in ICODE/DCODE space of Cortex-M3 processor and eSRAM_0 is located just above eSRAM_1 (adjacent to it).
0 SW_CC_ESRAMFWREMAP 0 This bit indicates that eSRAM_0 and eSRAM_1 are remapped to lCODE/DCODE space of the Cortex-M3 processor. If this bit is 1 and SW_CC_ESRAM1FWREMAP is 0, then eSRAM_0 is at location 0x00000000 and eSRAM_1 is always remapped to be just above eSRAM_0 (the two eSRAMs are adjacent in ICODE/DCODE space). Both eSRAMs also remain visible in SYSTEM space of the Cortex-M3 processor and remain visible at this location to all other (non-Cortex-M3 processor) masters. The bit definitions:
  • 0: No eSRAM remap is enabled. This means that eNVM (or MDDR) is present at location 0x00000000.
  • 1: eSRAM_0 and eSRAM_1 are remapped to location 0x00000000 of Cortex-M3 processor ICODE/DCODE space.
Table 5-7. ESRAM_MAX_LAT
Bit Number Name Reset Value Description
[31:6] Reserved 0 Reserved
[5:3] SW_MAX_LAT_ESRAM1 0x1 Defines the maximum number of cycles the processor bus will wait for eSRAM1 when it is being accessed by a master with a weighted round robin (WRR) priority scheme. The latency values are given in Table 5-8.
[2:0] SW_MAX_LAT_ESRAM0 0x1 Defines the maximum number of cycles the processor bus will wait for eSRAM0 when it is being accessed by a master with a WRR priority scheme. It is configurable from 1 to 8 (8, by default). The latency values are given in Table 5-8.

The following table gives eSRAM maximum latency values, where x is either 0 or 1.

Table 5-8. eSRAM Maximum Latency Values
SW_MAX_LAT_ESRAM<X> Latency
0 8 (default)
1 1
2 2
3 3
4 4
5 5
6 6
7 7
Table 5-9. ESRAM_PIPELINE_CR
Bit Number Name Reset Value Description
[31:1] Reserved 0 Reserved
0 ESRAM_PIPELINE_ENABLE 0x1 Controls the pipeline present in the read path of eSRAM memory. Allowed values:

0: Pipeline will be bypassed.

1: Pipeline will be present in the memory read path.
Table 5-10. ESRAM0_EDAC_CNT
Bit Number Name Reset Value Description
[31:16] ESRAM0_EDAC_CNT_2E 0 16-bit counter that counts the number of 2-bit uncorrected errors for eSRAM0. The counter will not roll back and will stay at its maximum value.
[15:0] ESRAM0_EDAC_CNT_1E 0 16-bit counter that counts the number of 1-bit corrected errors for eSRAM0. The counter will not roll back and will stay at its maximum value.
Important: See Table 5-19 to clear the counter.
Table 5-11. ESRAM1_EDAC_CNT
Bit Number Name Reset Value Description
[31:16] ESRAM1_EDAC_CNT_2E 0 16-bit counter that counts the number of 2-bit uncorrected errors for eSRAM1. The counter will not roll back and will stay at its maximum value.
[15:0] ESRAM1_EDAC_CNT_1E 0 16-bit counter that counts the number of 1-bit corrected errors for eSRAM1. The counter will not roll back and will stay at its maximum value.
Important: See Table 5-19 to clear the counter.
Table 5-12.  ESRAM0_EDAC_ADR
Bit Number Name Reset Value Description
[31:25] Reserved 0 Reserved
[25:13] ESRAM0_EDAC_2E_AD 0 Stores the address from eSRAM0 on which a 2-bit SECDED error has occurred.
[12:0] ESRAM0_EDAC_1E_AD 0 Stores the address from eSRAM0 on which a 1-bit SECDED error has occurred.
Table 5-13. ESRAM1_EDAC_ADR
Bit Number Name Reset Value Description
[31:25] Reserved 0 Reserved
[25:13] ESRAM1_EDAC_2E_AD 0 Stores the address from eSRAM1 on which a 2-bit SECDED error has occurred.
[12:0] ESRAM1_EDAC_1E_AD 0 Stores the address from eSRAM1 on which a 1-bit SECDED error has occurred.
Table 5-14. MM0_1_2_SECURITY
Bit Number Name Reset Value Description
[31:10] Reserved 0 Reserved
9 MM0_1_2_MS6_ALLOWED_W 1 Write security bits for Masters 0, 1, and 2 to Slave 6 (MSS DDR bridge). If not set, Masters 0, 1, and 2 will not have write access to Slave 6.
8 MM0_1_2_MS6_ALLOWED_R 1 Read security bits for Masters 0, 1, and 2 to Slave 6 (MSS DDR bridge). If not set, Masters 0, 1, and 2 will not have read access to Slave 6.
7 MM0_1_2_MS3_ALLOWED_W 1 Write security bits for Masters 0, 1, and 2 to Slave 3 (eNVM1). If not set, Masters 0, 1, and 2 will not have write access to Slave 3.
6 MM0_1_2_MS3_ALLOWED_R 1 Read security bits for Masters 0, 1 and 2 to Slave 3 (eNVM1). If not set, Masters 0, 1, and 2 will not have read access to Slave 3.
5 MM0_1_2_MS2_ALLOWED_W 1 Write security bits for Masters 0, 1, and 2 to Slave 2 (eNVM0]) If not set, Masters 0, 1, and 2 will not have write access to Slave 2.
4 MM0_1_2_MS2_ALLOWED_R 1 Read security bits for Masters 0, 1, and 2 to Slave 2 (eNVM0). If not set, Masters 0, 1, and 2 will not have read access to Slave 2.
3 MM0_1_2_MS1_ALLOWED_W 1 Write security bits for Masters 0, 1, and 2 to Slave 1 (eSRAM1). If not set, Masters 0, 1, and 2 will not have write access to Slave 1.
2 MM0_1_2_MS1_ALLOWED_R 1 Read security bits for Masters 0, 1, and 2 to Slave 1 (eSRAM1). If not set, Masters 0, 1, and 2 will not have read access to Slave 1.
1 MM0_1_2_MS0_ALLOWED_W 1 Write security bits for Masters 0, 1, and 2 to Slave 0 (eSRAM0). If not set, Masters 0, 1, and 2 will not have write access to Slave 0.
0 MM0_1_2_MS0_ALLOWED_R 1 Read security bits for Masters 0, 1, and 2 to Slave 0 (eSRAM0). If not set, Masters 0, 1, and 2 will not have read access to Slave 0.
Important: For more information on AHB Bus Matrix masters and slaves, see Figure 6-1.
Table 5-15. MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY
Bit Number Name Reset Value Description
[31:10] Reserved 0 Reserved
9 MM4_5_DDR_FIC_MS6_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to slave 6 (MSS DDR bridge). If not set, masters 4, 5 and DDR_FIC will not have write access to slave 6.
8 MM4_5_DDR_FIC_MS6_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to slave 6 (MSS DDR bridge). If not set, masters 4, 5, and DDR_FIC will not have read access to slave 6.
7 MM4_5_DDR_FIC_MS3_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to slave 3 (eNVM1). If not set, masters 4, 5, and DDR_FIC will not have write access to slave 3.
6 MM4_5_DDR_FIC_MS3_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to slave 3 (eNVM1). If not set, masters 4, 5, and DDR_FIC will not have read access to slave 3.
5 MM4_5_DDR_FIC_MS2_ALLOWED_W 1 Write Security Bits for masters 4, 5, and DDR_FIC to slave 2 (eNVM0). If not set, masters 4, 5, and DDR_FIC will not have write access to slave 2.
4 MM4_5_DDR_FIC_MS2_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to slave 2 (eNVM0). If not set, masters 4, 5, and DDR_FIC will not have read access to slave 2.
3 MM4_5_DDR_FIC_MS1_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to slave 1 (eSRAM1). If not set, masters 4, 5, and DDR_FIC will not have write access to slave 1.
2 MM4_5_DDR_FIC_MS1_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to slave 1 (eSRAM1). If not set, masters 4, 5, and DDR_FIC will not have read access to slave 1.
1 MM4_5_DDR_FIC_MS0_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to slave 0 (eSRAM0). If not set, masters 4, 5, and DDR_FIC will not have write access to slave 0.
0 MM4_5_DDR_FIC_MS0_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to slave 0 (eSRAM0). If not set, masters 4, 5, and DDR_FIC will not have read access to slave 0.
Important: For more information on AHB Bus Matrix masters and slaves, see Figure 6-1.
Table 5-16. MM3_6_7_8_SECURITY
Bit Number Name Reset Value Description
[31:10] Reserved 0 Reserved
9 MM3_6_7_8_MS6_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have write access to slave 6.
8 MM3_6_7_8_MS6_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have read access to slave 6.
7 MM3_6_7_8_MS3_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 3 (eNVM1). If not set, masters 3, 6, 7, and 8 will not have write access to slave 3.
6 MM3_6_7_8_MS3_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 3 (eNVM1). If not set, masters 3, 6, 7, and 8 will not have read access to slave 3.
5 MM3_6_7_8_MS2_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have write access to slave 2.
4 MM3_6_7_8_MS2_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 2.
3 MM3_6_7_8_MS1_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1). If not set, masters 3, 6, 7, and 8 will not have write access to slave 1.
2 MM3_6_7_8_MS1_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1). If not set, masters 3, 6, 7, and 8 will not have read access to slave 1.
1 MM3_6_7_8_MS0_ALLOWED_W 1 Write security bits for masters 3, 6, 7, and 8 to slave 0 (eSRAM0). If not set, masters 3, 6, 7, and 8 will not have write access to slave 0.
0 MM3_6_7_8_MS0_ALLOWED_R 1 Read security bits for masters 3, 6, 7, and 8 to slave 0 (eSRAM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 0.
Important: For more information on AHB Bus Matrix masters and slaves, see Figure 6-1.
Table 5-17. MM9_SECURITY
Bit Number Name Reset Value Description
[31:10] Reserved 0 Reserved
9 MM9_MS6_ALLOWED_W 1 Write security bits for master 9 to slave 6 (MSS DDR bridge). If not set, master 9 will not have write access to slave 6.
8 MM9_MS6_ALLOWED_R 1 Read security bits for master 9 to slave 6 (MSS DDR bridge). If not set, master 9 will not have read access to slave 6.
7 MM9_MS3_ALLOWED_W 1 Write security bits for master 9 to slave 3 (eNVM1). If not set, master 9 will not have write access to slave 3.
6 MM9_MS3_ALLOWED_R 1 Read security bits for master 9 to slave 3 (eNVM1). If not set, master 9 will not have read access to slave 3.
5 MM9_MS2_ALLOWED_W 1 Write security bits for master 9 to slave 2 (eNVM0). If not set, master 9 will not have write access to slave 2.
4 MM9_MS2_ALLOWED_R 1 Read security bits for master 9 to slave 2 (eNVM0). If not set, master 9 will not have read access to slave 2.
3 MM9_MS1_ALLOWED_W 1 Write security bits for master 9 to slave 1 (eSRAM1]) If not set, master 9 will not have write access to slave 1.
2 MM9_MS1_ALLOWED_R 1 Read security bits for master 9 to slave 1 (eSRAM1). If not set, master 9 will not have read access to slave 1.
1 MM9_MS0_ALLOWED_W 1 Write security bits for master 9 to slave 0 (eSRAM0). If not set, master 9 will not have write access to slave 0.
0 MM9_MS0_ALLOWED_R 1 Read security bits for master 9 to slave 0 (eSRAM0). If not set, master 9 will not have read access to slave 0.
Important: For more information on AHB Bus Matrix masters and slaves, see Figure 6-1.
Table 5-18. EDAC_SR
Bit Number Name Reset Value Description
[31:14] Reserved 0 Reserved
13 CAN_EDAC_2E 0 Updated by CAN when a 2-bit SECDED error has been detected for RAM memory.
12 CAN_EDAC_1E 0 Updated by CAN when a 1-bit SECDED error has been detected and is corrected for RAM memory.
11 USB_EDAC_2E 0 Updated by USB when a 2-bit SECDED error has been detected for RAM memory.
10 USB_EDAC_1E 0 Updated by USB when a 1-bit SECDED error has been detected and is corrected for RAM memory.
9 MAC_EDAC_RX_2E 0 Updated by Ethernet when a 2-bit SECDED error has been detected for Rx RAM memory.
8 MAC_EDAC_RX_1E 0 Updated by Ethernet when a 1-bit SECDED error has been detected and is corrected for Rx RAM memory.
7 MAC_EDAC_TX_2E 0 Updated by Ethernet when a 2-bit SECDED error has been detected for Tx RAM memory.
6 MAC_EDAC_TX_E 0 Updated by Ethernet when a 1-bit SECDED error has been detected and is corrected for Tx RAM memory.
5 Reserved 0 Reserved
4 Reserved 0 Reserved
3 ESRAM1_EDAC_2E 0 Updated by the eSRAM_1 controller when a 2-bit SECDED error has been detected for eSRAM1 memory.
2 ESRAM1_EDAC_1E 0 Updated by the eSRAM_1 Controller when a 1-bit SECDED error has been detected and is corrected for eSRAM1 memory.
1 ESRAM0_EDAC_2E 0 Updated by the eSRAM_0 controller when a 2-bit SECDED error has been detected for eSRAM0 memory.
0 ESRAM0_EDAC_1E 0 Updated by the eSRAM_0 controller when a 1-bit SECDED error has been detected and is corrected for eSRAM0 memory.
Table 5-19. CLR_EDAC_COUNTERS
Bit Number Name Reset Value Description
[31:14] Reserved 0 Reserved
13 CAN_EDAC_CNTCLR_2E 0 Generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the CAN_EDAC_CNT register.
12 CAN_EDAC_CNTCLR_1E 0 Generated to clear the 16-bit counter value in CAN corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the CAN_EDAC_CNT register.
11 USB_EDAC_CNTCLR_2E 0 Generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the USB_EDAC_CNT register.
10 USB_EDAC_CNTCLR_1E 0 Generated to clear the 16-bit counter value in USB corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the USB_EDAC_CNT register.
9 MAC_EDAC_RX_CNTCLR_2E 0 Generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the MAC_EDAC_RX_CNT register.
8 MAC_EDAC_RX_CNTCLR_1E 0 Generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_RX_CNT register.
7 MAC_EDAC_TX_CNTCLR_2E 0 Generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the MAC_EDAC_TX_CNT register.
6 MAC_EDAC_TX_CNTCLR_1E 0 Generated to clear the 16-bit counter value in Ethernet MAC Tx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_TX_CNT register.
5 Reserved 0 Reserved
4 Reserved 0 Reserved
3 ESRAM1_EDAC_CNTCLR_2E 0 Generated to clear the 16-bit counter value in ESRAM1 corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the Table 5-11 register.
2 ESRAM1_EDAC_CNTCLR_1E 0 Generated to clear the 16-bit counter value in eSRAM1 corresponding to count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the Table 5-11 register.
1 ESRAM0_EDAC_CNTCLR_2E 0 Generated to clear the 16-bit counter value in ESRAM0 corresponding to count value of EDAC 2bit Errors. This in turn clears the upper 16 bits of the Table 5-10 register.
0 ESRAM0_EDAC_CNTCLR_1E 0 Generated to clear the 16-bit counter value in ESRAM0 corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the Table 5-10 register.
Table 5-20. EDAC_IRQ_ENABLE_CR
Bit Number Name Reset Value Description
[31:15] Reserved 0 Reserved
14 MDDR_ECC_INT_EN 0 Allows the error EDAC for MDDR status update to be disabled. Allowed values:

0: MDDR_EDAC_2E_EN is disabled.

1: MDDR_EDAC_2E_EN is enabled.
13 CAN_EDAC_2E_EN 0 Allows the 2-bit error EDAC for CAN status update to be disabled. Allowed values:

0: CAN_EDAC_2E_EN is disabled.

1: CAN_EDAC_2E_EN is enabled.
12 CAN_EDAC_1E_EN 0 Allows the 1-bit error EDAC for CAN status update to be disabled. Allowed values:

0: CAN_EDAC_1E_EN is disabled.

1: CAN_EDAC_1E_EN is enabled.
11 USB_EDAC_2E_EN 0 Allows the 2-bit error EDAC for USB status update to be disabled. Allowed values:

0: USB_EDAC_2E_EN is disabled.

1: USB_EDAC_2E_EN is enabled.
10 USB_EDAC_1E_EN 0 Allows the 1-bit error EDAC for USB status update to be disabled. Allowed values:

0: USB_EDAC_1E_EN is disabled.

1: USB_EDAC_1E_EN is enabled.
9 MAC_EDAC_RX_2E_EN 0 Allows the 2-bit error EDAC for Ethernet Rx RAM status update to be disabled. Allowed values:

0: MAC_EDAC_RX_2E_EN is disabled.

1: MAC_EDAC_RX_2E_EN is enabled.
8 MAC_EDAC_RX_1E_EN 0 Allows the 1-bit error EDAC for Ethernet Rx RAM status update to be disabled. Allowed values:

0: MAC_EDAC_RX_1E_EN is disabled.

1: MAC_EDAC_RX_1E_EN is enabled.
7 MAC_EDAC_TX_2E_EN 0 Allows the 2-bit error EDAC for Ethernet Tx RAM status update to be disabled. Allowed values:

0: MAC_EDAC_TX_2E_EN is disabled.

1: MAC_EDAC_TX_2E_EN is enabled.
6 MAC_EDAC_TX_1E_EN 0 Allows the 1-bit error EDAC for Ethernet Tx RAM status update to be disabled. Allowed values:

0: MAC_EDAC_TX_1E_EN is disabled.

1: MAC_EDAC_TX_1E_EN is enabled.
5 Reserved 0 Reserved
4 Reserved 0 Reserved
3 ESRAM1_EDAC_2E_EN 0 Allows the 2-bit error EDAC for eSRAM1 status update to be disabled. Allowed values:

0: ESRAM1_EDAC_2E_EN is disabled.

1: ESRAM1_EDAC_2E_EN is enabled.
2 ESRAM1_EDAC_1E_EN 0 Allows the 1-bit error EDAC for eSRAM1 status update to be disabled. Allowed values:

0: ESRAM1_EDAC_1E_EN is disabled.

1: ESRAM1_EDAC_1E_EN is enabled.
1 ESRAM0_EDAC_2E_EN 0 Allows the 2-bit error EDAC for eSRAM0 status update to be disabled. Allowed values:

0: ESRAM0_EDAC_2E_EN is disabled.

1: ESRAM0_EDAC_2E_EN is enabled.
0 ESRAM0_EDAC_1E_EN 0 Allows the 1-bit error EDAC for eSRAM0 status update to be disabled. Allowed values:

0: ESRAM0_EDAC_1E_EN is disabled.

1: ESRAM0_EDAC_1E_EN is enabled.
Table 5-21. EDAC_CR
Bit Number Name Reset Value Description
[31:7] Reserved 0 Reserved.
6 CAN_EDAC_EN 0 Allows the EDAC for CAN to be disabled. Allowed values:

0: EDAC disabled

1: EDAC enabled
5 USB_EDAC_EN 0 Allows the EDAC for USB to be disabled. Allowed values:

0: EDAC disabled

1: EDAC enabled
4 MAC_EDAC_RX_EN 0 Allows the EDAC for Ethernet Rx RAM to be disabled. Allowed values:

0: Rx RAM EDAC disabled

1: Rx RAM EDAC enabled
3 MAC_EDAC_TX_EN 0 Allows the EDAC for Ethernet Tx RAM to be disabled. Allowed values:

0: Tx RAM EDAC disabled

1: Tx RAM EDAC enabled
2 Reserved 0 Reserved
1 ESRAM1_EDAC_EN 0 Allows the EDAC for eSRAM1 to be disabled. Allowed values:

0: EDAC disabled

1: EDAC enabled
0 ESRAM0_EDAC_EN 0 Allows the EDAC for eSRAM0 to be disabled. Allowed values:

0: EDAC disabled

1: EDAC enabled