5.2 Functional Description

The following table lists the sizes of the eSRAM blocks and their address range.

The following figure shows the eSRAM controller blocks and their connectivity in SmartFusion 2 FPGAs. Both eSRAMs and eSRAM controllers are identical in all design aspects.

M3_CLK is used within the MSS to clock the AHB bus matrix. For more information on M3_CLK, UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.

AHBL Interface: Each eSRAM controller is an AHB-Lite (AHBL) slave that provides access to the eSRAM block from the AHB bus matrix.

ECC Generator and Data MUX: In SECDED-ON mode, the ECC Generator generates the check bits for 32-bit data. For a 32-bit write from the AHBL interface, the input data AHB write data bus (HWDATA) is used to generate check bits. These check bits are appended to HWDATA and written to the memory. For 8-bit and 16-bit writes from the AHBL interface, a read-modify-write operation is used. This reads data from the 32-bit word, corrects if necessary, and then writes the new data value and ECC check bits.

In SECDED-OFF mode, if the memory access is within 32 KB memory, HWDATA is sent directly to the memory input. If the access is for additional 8 KB memory, then the address for a particular byte of HWDATA will be selected based on the shift address.

Address MUX: This utilizes the AHB address bus (HADDR) and HADDRU (an additional HADDR bit) for selecting upper 8 K bank of the RAM. Based on the FSM internal signals, output ADDR is generated and passed to the memory. The shifted address is also generated and used for multiplexing data.

FSM: This generates output signal HREADYOUT and internal signals that are used for multiplexing an address.

Pipeline: A pipeline stage in the read path of eSRAM and the master that accesses this path is configurable using the ESRAM_PIPELINE_ENABLE signal. When ESRAM_PIPELINE_ENABLE is High, there is an extra one clock cycle delay for the read operation to maximize operational frequency. At higher frequencies (> 100 MHz) of Cortex-M3 or other masters accessing eSRAM, the eSRAM operations need an extra clock cycle for the correct data transactions.

ECC Checker and AHB Read Data Bus (HRDATA) Generator: In SECDED-ON mode, the ECC Checker takes data (DO) from the memory as the input during the read or read-modify-write cycle and checks for errors. One-bit errors detected are corrected.

If errors of more than one bit are detected, they are not corrected. In SECDED-OFF mode, the read out data is directly given as output from this block. Error Status Signals are set if any errors are detected.

Error Status Signals: Error bits are inputs from the ECC Checker. If one error bit is High, it causes the EDAC_1E signal to be High. In this case, there is no HRESP as the error is corrected. If there are 2-bit errors, it cause the EDAC_2E signal to be High. In this case, HRESP is set High because the error is not corrected. The EDAC_1E and EDAC_2E signals are used to increment the ECC error counters within the SYSREG block (and the failing address is also passed to the SYSREG block). When the HRESET to ESRAMTOAHB is applied, it resets the EDAC address register which is maintained in ESRAMTOAHB and it does not clear the contents of SRAM. EDAC error counters are maintained in System Register, which can be cleared either through same HRESET or by setting the Table 5-19.