5.1 Features

  • Each eSRAM controller supports single bit error correction and dual bit error detection (SECDED).
  • Two modes of operation: SECDED-ON and SECDED-OFF.
  • The total amount of available eSRAM in each device is 64 KB in SECDED-ON mode and 80 KB in SECDED-OFF mode.
  • Each individual eSRAM block is 32 KB in SECDED-ON mode and 40 KB in 
SECDED-OFF mode, organized in a 2 × 4096 × 40 fashion.
  • Having two blocks (eSRAM_0 and eSRAM_1) maximizes hardware parallelism. For example, at the same instant that the Cortex-M3 processor is reading from eSRAM_0, the Ethernet controller can read from eSRAM_1 independently.
  • The eSRAM address space is byte, half-word (16-bit), and word (32-bit) addressable.
  • A pipeline is provided to address the latency issues at higher speeds of operation.

As shown in the following figure, the total available size of the eSRAM is divided into two equal-sized blocks: eSRAM_0 and eSRAM_1. eSRAM_0 and eSRAM_1 are connected to slave 0 and slave 1 on the AHB bus matrix through eSRAM controller 0 and eSRAM controller 1.

The eSRAM controller is designed to interface with an 8192 × 40 RAM, which is organized in a 
2 × 4096 × 40 fashion with five 8-bit byte lanes in total. The Cortex-M3 processor and other masters find the eSRAMs available as one contiguous area of memory.

The following figure depicts the connectivity of eSRAM_0 and eSRAM_1 to the AHB bus matrix.

Figure 5-1. eSRAM_0 and eSRAM_1 Connection to AHB Bus Matrix