13.2.1 Architecture Overview

The SPI controller supports master and slave modes of an operation.

  • In master mode, the SPI generates SPI_X_CLK, selects a slave using SPI_X_SS[x], transmits the data on SPI_X_DO, and receives the data on SPI_X_DI.
  • In slave mode, the SPI is selected by SPI_X_SS[0]. The SPI receives a clock on SPI_X_CLK and incoming data on SPI_X_DI.

The SPI peripherals consist mainly of the following components (see Figure 13-2).

  • Transmit and receive FIFOs
  • Configuration and control logic
  • SPI clock generator

The following figure shows the SPI controller block diagram.

Figure 13-2. SPI Controller Block Diagram
Important: X is used as a place holder for 0 or 1 in the register and signal descriptions. It indicates SPI _0 (on the APB_0 bus) or SPI_1 (on the APB_1 bus).