13.2.1.2 Configuration and Control Logic

The SPI peripheral can be configured for master or slave mode by using the mode bit of the SPI Table 13-9 register. The type of data transfer protocol can be configured by using the TRANSFPRTL bit of the SPI Table 13-9 register. The control logic monitors the number of data frames to be sent/received and enables the interrupts when the data frame transmission/reception is completed. During data frames transmission/reception, if a transmit under-run error/receive overflow error is detected, the Table 13-11 register is updated (see the Table 13-25 register for bit definitions).