13.2.1.1 Transmit and Receive FIFOs

The SPI controller embeds two 4 × 32 (depth × width) FIFOs for receive and transmit, as shown in Figure 13-2. These FIFOs are accessible through RX data and TX data registers (see the 13.4.3 SPI Register Details). Writing to the TX data register causes the data to be written to the transmit FIFO. This is emptied by the transmit logic. Similarly, reading from the RX data register causes the data to be read from the receive FIFO. The not-empty port of the receive FIFO and the not-full port of the transmit FIFO flags (of the FIFOs) are exposed as SPI_X_RXAVAIL (SPI has data to be read) and SPI_X_TXRFM (SPI has room for more data to send) ports. These are connected to the peripheral DMA (PDMA) engine to allow continuous DMA streaming for large SPI transfers and to help free up the Cortex-M3 processor.