22.3.2.2.2 Soft Processor in FPGA Fabric

If MSS peripheral interrupt sources to be used as an interrupt sources to a soft processor within the FPGA fabric, the following steps to be implemented in soft processor:

Step 1 - Enabling the MSS to the Fabric Interrupt

Set M2F interrupt enable register bit of MSS peripheral in <Table 22-7> or <Table 22-8> registers.

For example, to enable Timer1 MSS to fabric interrupt (MSS_INT_M2F [10]), TIMER1_INTR_ENBL bit in Table 22-7 register must be set.

Step 2 - Initialize and Configure Peripheral

Refer to peripheral chapters for initialization, configuration, and use model.

Step 3 - Enable Peripheral Interrupt

Refer to peripheral chapters for interrupt enable registers.

For example, you need to set TIMxINTEN bit in Table 18-8 register for Timer1 interrupt.

Important: Once MSS to Fabric Interrupt is asserted, the interrupt remains asserted until the user logic (soft processor /FSM) clears the appropriate MSS peripheral interrupt clear register.

Steps 4 - Clear Peripheral Interrupt

Refer to peripheral chapters for interrupt clear registers.

For example, you need to set TIMx_RIS bit in Table 18-9 register for clearing Timer1 interrupt.