9.2.3.2.2 Host Mode

If the reset bit in POWER_REG is set while the USB controller is in Host mode, the USB controller generates reset signaling on the bus. If the HS Enab bit in POWER_REG is set, it tries to negotiate for a high speed operation.

The Cortex-M3 processor or fabric master must keep the reset bit set for at least 20 ms to ensure the correct resetting of the target device.

After the Cortex-M3 processor or fabric master clears the bit, the USB controller starts the frame counter and transaction scheduler. Whether a high speed operation is selected, is indicated by the HS mode bit of 9.3.5.2 POWER_REG Bit Definitions (Table 9-11).