9.3.5.2 POWER_REG Bit Definitions

Table 9-11. POWER_REG (0x40043001)
Bit Number	Name	Reset Value	Function
7	ISO Update	0	When set by the Arm® Cortex®-M3 processor (or fabric master), the USB controller waits for an SOF token from the time TxPktRdy is set before sending the packet. If an IN token is received before an SOF token, a zero length data packet will be sent. Only valid in Peripheral mode. Also, this bit only affects endpoints performing ISO transfers.
6	Soft Conn	0	If the soft connect/disconnect feature is enabled, the USB D+/D- lines are enabled when this bit is set by the Cortex-M3 processor (or fabric master) and tristated when this bit is cleared by the Cortex-M3 processor (or fabric master). Only valid in Peripheral mode.
5	HS Enab	1	When set by CPU, the USB controller negotiates for High speed mode when the device is reset by the hub. If not set, the device will only operate in Full speed mode.
4	HS Mode	0	When set, this read-only bit indicates High speed mode successfully negotiated during USB reset. In Peripheral mode, becomes valid when USB reset completes (as indicated by USB reset interrupt). In Host mode, becomes valid when the reset bit is cleared. Remains valid for the duration of the session. Allowance is made for Tiny-J signaling in determining the transfer speed to select.
3	Reset	0	This bit is set when reset signaling is present on the bus. This bit is read/write from the Cortex-M3 processor (or fabric master) in Host mode but read-only in Peripheral mode.
2	Resume	0	Set by the Cortex-M3 processor (or fabric master) to generate resume signaling when the device is in Suspend mode. In Peripheral mode, the Cortex-M3 processor (or fabric master) should clear this bit after 10 ms (a maximum of 15 ms), to end resume signaling. In Host mode, the Cortex-M3 processor (or fabric master) should clear this bit after 20 ms.
1	Suspend Mode	0	In Host mode, this bit is set by the Cortex-M3 processor (or fabric master) to enter Suspend mode. In Peripheral mode, this bit is set on entry into Suspend mode. It is cleared when the Cortex-M3 processor (or fabric master) reads the interrupt register, or sets the resume bit above.
0	Enable SuspendM	0	Set by the Cortex-M3 processor (or fabric master) to enable the SUSPENDM output.

7

ISO Update

0

When set by the Arm® Cortex®-M3 processor (or fabric master), the USB controller waits for an SOF token from the time TxPktRdy is set before sending the packet. If an IN token is received before an SOF token, a zero length data packet will be sent.

Only valid in Peripheral mode. Also, this bit only affects endpoints performing ISO transfers.

6

Soft Conn

0

If the soft connect/disconnect feature is enabled, the USB D+/D- lines are enabled when this bit is set by the Cortex-M3 processor (or fabric master) and tristated when this bit is cleared by the Cortex-M3 processor (or fabric master).

Only valid in Peripheral mode.

5

HS Enab

1

When set by CPU, the USB controller negotiates for High speed mode when the device is reset by the hub. If not set, the device will only operate in Full speed mode.

4

HS Mode

0

When set, this read-only bit indicates High speed mode successfully negotiated during USB reset. In Peripheral mode, becomes valid when USB reset completes (as indicated by USB reset interrupt). In Host mode, becomes valid when the reset bit is cleared. Remains valid for the duration of the session.

Allowance is made for Tiny-J signaling in determining the transfer speed to select.

3

Reset

0

This bit is set when reset signaling is present on the bus.

This bit is read/write from the Cortex-M3 processor (or fabric master) in Host mode but read-only in Peripheral mode.

2

Resume

0

Set by the Cortex-M3 processor (or fabric master) to generate resume signaling when the device is in Suspend mode. In Peripheral mode, the Cortex-M3 processor (or fabric master) should clear this bit after 10 ms (a maximum of 15 ms), to end resume signaling. In Host mode, the Cortex-M3 processor (or fabric master) should clear this bit after 20 ms.

1

Suspend Mode

0

In Host mode, this bit is set by the Cortex-M3 processor (or fabric master) to enter Suspend mode. In Peripheral mode, this bit is set on entry into Suspend mode. It is cleared when the Cortex-M3 processor (or fabric master) reads the interrupt register, or sets the resume bit above.

0

Enable SuspendM

0

Set by the Cortex-M3 processor (or fabric master) to enable the SUSPENDM output.