31.8.5 Network Control Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | NCR |
Offset: | 0x1000 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
LPI | FNP | TXPBPF | ENPBPR | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
SRTSM | TXZQPF | TXPF | THALT | TSTART | BP | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WESTAT | INCSTAT | CLRSTAT | MPE | TXEN | RXEN | LBL | |||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 19 – LPI Low Power Idle Transmission Enable
When this bit is set, LPI (low power idle) is immediately transmitted. LPI is transmitted even if transmit enable bit NCR.TXEN is disabled.
Setting this bit also sends a pause signal to the transmit datapath.
Bit 18 – FNP Flush Next Packet
Writing a '1' to this bit will flush the next packet from the System RAM. Flushing the next packet will only take effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.
Bit 17 – TXPBPF Transmit PFC Priority-based Pause Frame
Takes the values stored in the Transmit PFC Pause Register.
Bit 16 – ENPBPR Enable PFC Priority-based Pause Reception
Writing a '1' to this bit enables PFC Priority Based Pause Reception capabilities, enabling PFC negotiation and recognition of priority-based pause frames.
Value | Description |
---|---|
0 | Normal operation |
1 | PFC Priority-based Pause frames are recognized. |
Bit 15 – SRTSM Store Receive Time Stamp to Memory
Writing a '1' to this bit causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point.
Note that bit RFCS in register NCFGR may not be set to 1 when the timer should be captured.
Value | Description |
---|---|
0 | Normal operation |
1 | All received frames' CRC is replaced with a time stamp. |
Bit 12 – TXZQPF Transmit Zero Quantum Pause Frame
Writing a '1' to this bit causes a pause frame with zero quantum to be transmitted.
Writing a '0' to this bit has no effect.
Bit 11 – TXPF Transmit Pause Frame
Writing one to this bit causes a pause frame to be transmitted.
Writing a '0' to this bit has no effect.
Bit 10 – THALT Transmit Halt
Writing a '1' to this bit halts transmission as soon as any ongoing frame transmission ends.
Writing a '0' to this bit has no effect.
Bit 9 – TSTART Start Transmission
Writing a '1' to this bit starts transmission.
Writing a '0' to this bit has no effect.
Bit 8 – BP Back Pressure
In 10M or 100M half duplex mode, writing a '1' to this bit forces collisions on all received frames.
Value | Description |
---|---|
0 | Frame collisions are not forced. |
1 | Frame collisions are forced in 10M and 100M half duplex mode. |
Bit 7 – WESTAT Write Enable for Statistics Registers
Writing a '1' to this bit makes the statistics registers writable for functional test purposes.
Value | Description |
---|---|
0 | Statistics Registers are write-protected. |
1 | Statistics Registers are write-enabled. |
Bit 6 – INCSTAT Increment Statistics Registers
Writing a '1' to this bit increments all Statistics Registers by one for test purposes.
Writing a '0' to this bit has no effect.
This bit will always read '0'.
Bit 5 – CLRSTAT Clear Statistics Registers
Writing a '1' to this bit clears the Statistics Registers.
Writing a '0' to this bit has no effect.
This bit will always read '0'.
Bit 4 – MPE Management Port Enable
Writing a '1' to this bit enables the Management Port.
Writing a '0' to this bit disables the Management Port, and forces MDIO to high impedance state and MDC to low impedance.
Value | Description |
---|---|
0 | Management Port is disabled. |
1 | Management Port is enabled. |
Bit 3 – TXEN Transmit Enable
Writing a '1' to this bit enables the ETH transmitter to send data.
Value | Description |
---|---|
0 | Transmit is disabled. |
1 | Transmit is enabled. |
Bit 2 – RXEN Receive Enable
Writing a '1' to this bit enables the ETH to receive data.
Value | Description |
---|---|
0 | Receive is disabled. |
1 | Receive is enabled. |
Bit 1 – LBL Loop Back Local
Writing '1' to this bit connects ETH_TX to ETH_RX, ETH_TXEN to ETH_RXDV, and forces full duplex mode.
ETH_RXCK and ETH_TXCK may malfunction as the ETH is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.
Value | Description |
---|---|
0 | Loop back local is disabled. |
1 | Loop back local is enabled. |