31.8.113 ETH Interrupt Enable Register Priority Queue x

The following values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Table 31-128. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	IERQ
Offset:	0x1600 + (n-1)*0x04 [n=1..5]
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					HRESP	ROVR
Access					W	W
Reset					–	–


Bit	7	6	5	4	3	2	1	0
	TCOMP	TFC	RLEX	TUR	TXUBR	RXUBR	RCOMP
Access	W	W	W	W	W	W	W
Reset	–	–	–	–	–	–	–

Bit 11 – HRESP HRESP Not OK

Bit 10 – ROVR Receive Overrun

Bit 7 – TCOMP Transmit Complete

Bit 6 – TFC Transmit Frame Corruption Due to AXI Error

Bit 5 – RLEX Retry Limit Exceeded or Late Collision

Bit 4 – TUR Transmit Underrun

Bit 3 – TXUBR TX Used Bit Read

Bit 2 – RXUBR RX Used Bit Read

Bit 1 – RCOMP Receive Complete

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.