31.8.109 ETH Receive Buffer Queue Base Address Register Priority Queue x

These registers hold the start address of the receive buffer queues (receive buffers descriptor lists) for the additional queues used when priority queues are employed.

Table 31-124. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RBPQB
Offset:	0x1480 + (n-1)*0x04 [n=1..5]
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	RXBQBA[29:22]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RXBQBA[21:14]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RXBQBA[13:6]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RXBQBA[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0

Bits 31:2 – RXBQBA[29:0] Receive Buffer Queue Base Address

Holds the address of the start of the receive queue.