31.8.9 ETH DMA Configuration Register

Table 31-24. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	DCFGR
Offset:	0x1010
Reset:	0x00020004
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
								DDRP
Access								R/W
Reset								0


Bit	23	22	21	20	19	18	17	16
	DRBS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	1	0


Bit	15	14	13	12	11	10	9	8
					TXCOEN	TXPBMS	RXBMS[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	1	1	1


Bit	7	6	5	4	3	2	1	0
	ESPA	ESMA		FBLDO[4:0]
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0	0		0	0	1	0	0

Bit 24 – DDRP DMA Discard Receive Packets

A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode.

Value	Description
0	Received packets are stored in the SRAM based packet buffer until next AXI buffer resource becomes available.
1	Receive packets from the receiver packet buffer memory are automatically discarded when no AXI resource is available.

Bits 23:16 – DRBS[7:0] DMA Receive Buffer Size

These bits defined by these bits determines the size of buffer to use in main AXI system memory when writing received data.

The value is defined in multiples of 64 bytes. For example:

0x02: 128 bytes
0x18: 1536 bytes (1 × max length frame/buffer)
0xA0: 10240 bytes (1 × 10K jumbo frame/buffer)

Warning: Do not write 0x00 to this bit field.

Bit 11 – TXCOEN Transmitter Checksum Generation Offload Enable

Transmitter IP, TCP and UDP checksum generation offload enable.

Value	Description
0	Frame data is unaffected.
1	The transmitter checksum generation engine calculates and substitutes checksums for transmit frames.

Bit 10 – TXPBMS Transmitter Packet Buffer Memory Size Select

When written to zero, the amount of memory used for the transmit packet buffer is reduced by 50%. This reduces the amount of memory used by the ETH.

It is important to write this bit to '1' if the full configured physical memory is available. The value in parentheses represents the size that would result for the default maximum configured memory size of 4 KBytes.

Value	Description
0	Top address bits not used. (2KByte used.)
1	Full configured addressable space (4KBytes) used.

Bits 9:8 – RXBMS[1:0] Receiver Packet Buffer Memory Size Select

The default receive packet buffer size is FULL=8 Kbytes. The table below shows how to configure this memory to FULL, HALF, QUARTER or EIGHTH of the default size.

Value	Name	Description
0	EIGHTH	8/8 Kbyte Memory Size
1	QUARTER	8/4 Kbytes Memory Size
2	HALF	8/2 Kbytes Memory Size
3	FULL	8 Kbytes Memory Size

Bit 7 – ESPA Endian Swap Mode Enable for Packet Data Accesses

Value	Description
0	Little endian mode for AXI transfers selected.
1	Big endian mode for AXI transfers selected.

Bit 6 – ESMA Endian Swap Mode Enable for Management Descriptor Accesses

Value	Description
0	Little endian mode for AXI transfers selected.
1	Big endian mode for AXI transfers selected.

Bits 4:0 – FBLDO[4:0] Fixed Burst Length for DMA Data Operations

Selects the burst length to attempt to use on the AXI when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AXI transfers are used.

One-hot priority encoding enforced automatically on register writes as follows. ‘x’ represents don’t care.

Value	Name	Description
0	-	Reserved
1	SINGLE	00001: Always use SINGLE AXI bursts
2	-	Reserved
4	INCR4	001xx: Attempt to use INCR4 AXI bursts (Default)
8	INCR8	01xxx: Attempt to use INCR8 AXI bursts
16	INCR16	1xxxx: Attempt to use INCR16 AXI bursts