31.8.2 ETH Control B Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | CTRLB |
Offset: | 0x0004 |
Reset: | 0x000000C0 |
Property: | PAC Write Protected, Enable Write-Protected |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TSUINC[1:0] | TSUMS | TSUCLKREQ | |||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 1 | 0 | 0 |
Bits 7:6 – TSUINC[1:0] Timer Adjust Mode
An alternative way of controlling the way the timer increment register
2’b11 = timer register increments as normal
2’b10 = timer register increments by an additional nanosecond
2’b01 = timer increments by a nanosecond less.
2’b00 = uses TSUINC
Bit 5 – TSUMS Timer Adjust
Value | Description |
---|---|
0 | The timer register increments as normal, but the timer value is copied to the sync strobe register |
1 | The “nanoseconds” timer register is cleared and the “seconds” timer register is incremented with each clock cycle. |
Bit 2 – TSUCLKREQ TSU GCLK Request
Value | Description |
---|---|
0 | no clock request. |
1 | GCLK_ETH_TSU clock request |