31.8.1 ETH Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0000 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the ETH running in standby mode.
| Value | Description |
|---|---|
| 0 | The ETH module is disabled in Standby Sleep mode, clock requests are de-asserted after any pending bus transactions or requests are complete. |
| 1 | The ETH module continues to run in Standby Sleep mode. |
Bit 1 – ENABLE ETH Clock Enable
Changing the state of this bit from ‘0’ to ‘1’ or ‘1’ to ‘0’ sets the SYNCBUSY.ENABLE bit to 1. The SYNCBUSY.ENABLE bit stays asserted until the module is either completely enabled or completely disabled.
Note: If the ETH is enabled the user
should ensure the ETH finishes all tasks before writing this bit to ‘0’.
| Value | Description |
|---|---|
| 0 | Disable module. System clock is only requested for bus transactions. GCLK is never requested, turn off module, disable clocks, disable interrupt event generation. |
| 1 | Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests. |