33.22.11 PMC Main System Bus Clock Register

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode register.

Name:	PMC_MCKR
Offset:	0x0030
Reset:	0x00000001
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
								H32MXDIV
Access								R/W
Reset								0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				PLLADIV2			MDIV[1:0]
Access				R/W			R/W	R/W
Reset				0			0	0


Bit	7	6	5	4	3	2	1	0
		PRES[2:0]					CSS[1:0]
Access		R/W	R/W	R/W			R/W	R/W
Reset		0	0	0			0	1

Bit 24 – H32MXDIV AHB 32-bit Matrix Divisor

Value	Name	Description
0	H32MXDIV1	The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency. It is possible only if the AHB 64-bit Matrix frequency does not exceed 83 MHz.
1	H32MXDIV2	The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2.

Bit 12 – PLLADIV2 PLLA Divisor by 2

Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.

Bits 9:8 – MDIV[1:0] Main System Bus Clock Division

Value	Name	Description
0	EQ_PCK	Main System Bus clock is Prescaler Output clock divided by 1. Warning: DDRCK is not available.
1	PCK_DIV2	Main System Bus clock is Prescaler Output clock divided by 2. DDRCK is equal to MCK.
2	PCK_DIV4	Main System Bus clock is Prescaler Output clock divided by 4. DDRCK is equal to MCK.
3	PCK_DIV3	Main System Bus clock is Prescaler Output clock divided by 3. DDRCK is equal to MCK.

Bits 6:4 – PRES[2:0] Main System Bus/Processor Clock Prescaler

Value	Name	Description
0	CLOCK	Selected clock
1	CLOCK_DIV2	Selected clock divided by 2
2	CLOCK_DIV4	Selected clock divided by 4
3	CLOCK_DIV8	Selected clock divided by 8
4	CLOCK_DIV16	Selected clock divided by 16
5	CLOCK_DIV32	Selected clock divided by 32
6	CLOCK_DIV64	Selected clock divided by 64
7	–	Reserved

Bits 1:0 – CSS[1:0] Main System Bus/Processor Clock Source Selection

Value	Name	Description
0	SLOW_CLK	Slow clock is selected
1	MAIN_CLK	Main clock is selected
2	PLLA_CLK	PLLACK is selected
3	UPLL_CLK	UPLL Clock is selected