33.22.13 PMC Programmable Clock Register
| Name: | PMC_PCKx |
| Offset: | 0x40 + x*0x04 [x=0..2] |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRES[7:4] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRES[3:0] | CSS[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 11:4 – PRES[7:0] Programmable Clock Prescaler
Bits 2:0 – CSS[2:0] Main System Bus Clock Source Selection
| Value | Name | Description |
|---|---|---|
| 0 | SLOW_CLK | Slow clock is selected. |
| 1 | MAIN_CLK | Main clock is selected. |
| 2 | PLLA_CLK | PLLACK is selected. |
| 3 | UPLL_CLK | UPLL clock is selected. |
| 4 | MCK_CLK | Main System Bus clock is selected. |
| 5 | AUDIO_CLK | Audio PLL clock is selected. |