33.22.10 PMC Clock Generator PLLA Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
| Name: | CKGR_PLLAR |
| Offset: | 0x0028 |
| Reset: | 0x00003F00 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ONE | MULA[6] | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MULA[5:0] | OUTA[3:2] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OUTA[1:0] | PLLACOUNT[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVA | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 29 – ONE Must Be Set to 1
Bit 29 must always be set to 1 when programming CKGR_PLLAR.
Bits 24:18 – MULA[6:0] PLLA Multiplier
| Value | Description |
|---|---|
| 0 | The PLLA is disabled. |
| 1–127 | The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1. |
Bits 17:14 – OUTA[3:0] PLLA Clock Frequency Range
Bits 13:8 – PLLACOUNT[5:0] PLLA Counter
Specifies the number of Slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
Bit 0 – DIVA Divider A
| Value | Description |
|---|---|
| 0 |
PLLA is disabled. |
| 1 |
Divider is bypassed and the PLL input entry is Main clock (MAINCK). |