33.22.5 PMC Peripheral Clock Disable Register 0

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

Name: PMC_PCDR0
Offset: 0x0014
Reset: –
Property: Write-only

Bit 3130292827262524 
 PID31PID30PID29PID28PID27PID26PID25PID24 
Access WWWWWWWW 
Reset –––––––– 
Bit 2322212019181716 
 PID23PID22PID21PID20PID19PID18PID17PID16 
Access WWWWWWWW 
Reset –––––––– 
Bit 15141312111098 
 PID15PID14PID13PID12PID11PID10PID9PID8 
Access WWWWWWWW 
Reset –––––––– 
Bit 76543210 
 PID7PID6PID5PID4PID3PID2   
Access WWWWWW 
Reset –––––– 

Bits 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Disable

PID2 to PID31 refer to identifiers as defined in section “Peripheral Identifiers”. Other peripherals can be disabled in PMC_PCDR1.
ValueDescription
0

No effect.
1

Disables the corresponding peripheral clock.