33.22.37 PMC Asynchronous Partial Wake-Up Control Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode register.
| Name: | PMC_SLPWKCR |
| Offset: | 0x0148 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SLPWKSR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ASR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMD | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PID[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 28 – SLPWKSR Asynchronous Partial Wake-Up Status Register
Not all PIDs can be configured with asynchronous partial wake-up.
Only the following PIDs can be configured with asynchronous partial wake-up: FLEXCOMx, SPIx, TWIx, UARTx and ADC.
| Value | Description |
|---|---|
| 0 |
The asynchronous partial wake-up function of the peripheral is disabled. |
| 1 |
The asynchronous partial wake-up function of the peripheral is enabled. |
Bit 16 – ASR Activity Status Register
Not all PIDs can be configured with asynchronous partial wake-up.
Only the following PIDs can be configured with asynchronous partial wake-up: FLEXCOMx, SPIx, TWIx, UARTx and ADC.
| Value | Description |
|---|---|
| 0 |
The peripheral x is not currently active; the asynchronous partial wake-up function can be activated. |
| 1 |
The peripheral x is currently active; the asynchronous partial wake-up function must not be activated. |
Bit 12 – CMD Command
| Value | Description |
|---|---|
| 0 |
Read mode |
| 1 |
Write mode |
Bits 6:0 – PID[6:0] Peripheral ID
Peripheral ID selection from PID2 to the maximum PID number. This refers to identifiers as defined in the section “Peripheral Identifiers”.