33.22.1 PMC System Clock Enable Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | PMC_SCER |
| Offset: | 0x0000 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ISCCK | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCK2 | PCK1 | PCK0 | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UDP | UHP | LCDCK | DDRCK | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
Bit 18 – ISCCK ISC Clock Enable
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
Enables the ISC clock. |
Bits 8, 9, 10 – PCKx Programmable Clock x Output Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the corresponding Programmable Clock output. |
Bit 7 – UDP USB Device Clock Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the USB Device clock. |
Bit 6 – UHP USB Host OHCI Clocks Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the UHP48M and UHP12M OHCI clocks. |
Bit 3 – LCDCK MCK2x Clock Enable
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
Enables the MCK2x clock. |
Bit 2 – DDRCK DDR Clock Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the DDR clock. |