2.1.11 CoreAPB3_0

CoreAPB3_0 is configured as shown in the Figure 2-16 to connect the peripherals CoreSPI, Core_SPI_Flash, CoreGPIO, PF_SYSTEM_SERVICES, and CoreUARTapb as slaves.

The following are the features of CoreAPB3 configuration.

  • APB Master Data bus width: 32 bit
  • A number of address bits are driven by the master: 16. The Mi-V processor addresses slaves using 16-bit addressing, so the final address for these slaves translates to 0x6000_0000, 0x6000_1000, and 0x6000_2000
  • Enabled APB Slave Slots: S0, S1, S2, S3, and S4 (for CoreUARTapb, CoreSPI, Core_SPI_Flash, CoreGPIO, and PF_SYSTEM_SERVICES respectively)

The following figure shows the CoreAPB3 configuration.

Figure 2-16. CoreAPB3 Configuration